Datasheet

Datasheet, Volume 2 563
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Processor Uncore Configuration Registers
4.8.28 TXEQ_LVL3_0 Register
4.8.29 FWDC_LCPKAMP_CFG Register
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TXEQ_LVL3_0
Bus: 1 Device: 8 Function: 4 Offset: 7FCh
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RWS-L 3Fh
bndl4
Transmit Equalization Level3 coefficients for FIR settings
23:18 RWS-L 3Fh bndl3
17:12 RWS-L 3Fh bndl2
11:6 RWS-L 3Fh bndl1
5:0 RWS-L 3Fh bndl0
FWDC_LCPKAMP_CFG
Bus: 1 Device: 8 Function: 4 Offset: 390h
Bus: 1 Device: 9 Function: 4 Offset: 390h
Bit Attr
Reset
Value
Description
31:17 RV 0h Reserved
16 RWS-L 1h
fwdc lcampen
Enable signal for LC peak amplifier. When this path is enabled, the other parallel
forwarded clock path is disabled
0 = LC peak amplifier is disabled
1 = LC peak amplifier is enabled
15:13 RV 0h Reserved
12:8 RWS-L 8h
fwdc lcampcapctl
LC peak amplifier capacitor load control signals.
8 Gbps = 8h (default)
6.4 Gbps = 1Fh
7:6 RV 0h Reserved
5:4 RWS-L 0h
fwdc lcampfbkctl
LC peak amplifier miller cap control signals.
3:2 RWS-L 0h
fwdc lcampibiasctl
LC peak amplifier pmos load control signals.
1:0 RWS-L 0h
fwdc lcamppbiasctl
LC peak amplifier tail current bias control signals