Datasheet

Processor Uncore Configuration Registers
562 Datasheet, Volume 2
4.8.25 TXEQ_LVL1_1 Register
4.8.26 TXEQ_LVL2_0 Register
4.8.27 TXEQ_LVL2_1 Register
TXEQ_LVL1_1
Bus: 1 Device: 8 Function: 4 Offset: 7F0h
Bit Attr
Reset
Value
Description
31 RV 0h Reserved
30 RV 0h Reserved
29:24 RWS-L 3Fh
bndl9
Transmit Equalization Level1 coefficients for FIR settings
23:18 RWS-L 3Fh bndl8
17:12 RWS-L 3Fh bndl7
11:6 RWS-L 3Fh bndl6
5:0 RWS-L 3Fh bndl5
TXEQ_LVL2_0
Bus: 1 Device: 8 Function: 4 Offset: 7F4h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RWS-L 3Fh
bndl4
Transmit Equalization Level2 coefficients for FIR settings
23:18 RWS-L 3Fh bndl3
17:12 RWS-L 3Fh bndl2
11:6 RWS-L 3Fh bndl1
5:0 RWS-L 3Fh bndl0
TXEQ_LVL2_1
Bus: 1 Device: 8 Function: 4 Offset: 7F8h
Bit Attr
Reset
Value
Description
31 RV 0h Reserved
30 RV 0h Reserved
29:24 RWS-L 3Fh
bndl9
Transmit Equalization Level2 coefficients for FIR settings
23:18 RWS-L 3Fh bndl8
17:12 RWS-L 3Fh bndl7
11:6 RWS-L 3Fh bndl6
5:0 RWS-L 3Fh bndl5