Datasheet

Datasheet, Volume 2 561
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Processor Uncore Configuration Registers
4.8.22 TXEQ_LVL0_0 Register
4.8.23 TXEQ_LVL0_1 Register
4.8.24 TXEQ_LVL1_0 Register
TXEQ_LVL0_0
Bus: 1 Device: 8 Function: 4 Offset: 7E4h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RWS-L 3Fh
bndl4
Transmit Equalization Level0 coefficients for FIR settings
23:18 RWS-L 3Fh bndl3
17:12 RWS-L 3Fh bndl2
11:6 RWS-L 3Fh bndl1
5:0 RWS-L 3Fh bndl0
TXEQ_LVL0_1
Bus: 1 Device: 8 Function: 4 Offset: 7E8h
Bit Attr
Reset
Value
Description
31 RV 0h Reserved
30 RV 0h Reserved
29:24 RWS-L 3Fh
bndl9
Transmit Equalization Level0 coefficients for FIR settings
23:18 RWS-L 3Fh bndl8
17:12 RWS-L 3Fh bndl7
11:6 RWS-L 3Fh bndl6
5:0 RWS-L 3Fh bndl5
TXEQ_LVL1_0
Bus: 1 Device: 8 Function: 4 Offset: 7ECh
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RWS-L 3Fh
bndl4
Transmit Equalization Level1 coefficients for FIR settings
23:18 RWS-L 3Fh bndl3
17:12 RWS-L 3Fh bndl2
11:6 RWS-L 3Fh bndl1
5:0 RWS-L 3Fh bndl0