Datasheet

Processor Uncore Configuration Registers
560 Datasheet, Volume 2
4.8.21 TXALIGN_EN Register
5:0 RWS-L 12h
TL0sWake: TL0S_WAKE
If # of links supported is greater than 0, then Link Select must always be used to
display the current read value for this field.
There is a write dependency for this field based on the value of Can Control
Multiple Links?
If Can Control Multiple Links? = 0, then Link Select must be used to only write to
the selected Link.
If Can Control Multiple Links? = 1, then every Link selected in Link Control will
receive the written value.
Intel QPI Behavior
Local L0s Wake-up time the remote agent must not violate. Set by firmware on
both link ports prior to entering L0s.
This field is at 16 UI granularity and the value of this field is (count + 1)*16 UI
A value is 0 indicates that L0s is not supported on the local agent.
TXALIGN_EN
Bus: 1 Device: 8 Function: 4 Offset: 648h
Bit Attr
Reset
Value
Description
31 RWS-L 0h override_enable
30:26 RV 0h Reserved
25 RWS-L 1h
lane19
Enable TX data alignment
24 RWS-L 1h lane18
23 RWS-L 1h lane17
22 RWS-L 1h lane16
21 RWS-L 1h lane15
20 RWS-L 1h lane14
19 RWS-L 1h lane13
18 RWS-L 1h lane12
17 RWS-L 1h lane11
16 RWS-L 1h lane10
15:10 RV 0h Reserved
9RWS-L1hlane9
8RWS-L1hlane8
7RWS-L1hlane7
6RWS-L1hlane6
5RWS-L1hlane5
4RWS-L1hlane4
3RWS-L1hlane3
2RWS-L1hlane2
1RWS-L1hlane1
0RWS-L1hlane0
QPIREUT_PM_R0
Bus: 1 Device: 8 Function: 3 Offset: 190h
Bus: 1 Device: 9 Function: 3 Offset: 190h
Bit Attr
Reset
Value
Description