Datasheet

Processor Integrated I/O (IIO) Configuration Registers
56 Datasheet, Volume 2
3.2.4.18 MBAS—Memory Base Register
3.2.4.19 MLIM—Memory Limit Register
MBAS
Bus: 0 Device: 0 Function: 0 Offset: 20h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 20h
Bus: 0 Device: 2 Function: 0–3 Offset: 20h
Bus: 0 Device: 3 Function: 0–3 Offset: 20h
Bit Attr
Reset
Value
Description
15:4 RW FFFh
Memory Base Address
This bit corresponds to A[31:20] of the 32-bit memory window’s base address of
the PCI Express port. See also the MLIM register description.
3:0 RV 0h Reserved
MLIM
Bus: 0 Device: 0 Function: 0 Offset: 22h (PCIe* MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 22h
Bus: 0 Device: 2 Function: 0–3 Offset: 22h
Bus: 0 Device: 3 Function: 0–3 Offset: 22h
Bit Attr
Reset
Value
Description
15:4 RW 000h
Memory Limit Address
This field corresponds to A[31:20] of the 32-bit memory window’s limit address
that corresponds to the upper limit of the range of memory accesses that will be
passed by the PCI Express bridge.The Memory Base and Memory Limit registers
define a memory mapped I/O non-prefetchable address range (32-bit addresses)
and the IIO directs accesses in this range to the PCI Express port based on the
following formula:
MEMORY_BASE  A[31:20]  MEMORY_LIMIT
The upper 12 bits of both the Memory Base and Memory Limit registers are read/
write and correspond to the upper 12 address bits – A[31:20] of 32-bit addresses.
Thus, the bottom of the defined memory address range will be aligned to a 1 MB
boundary and the top of the defined memory address range will be one less than a
1 MB boundary. Refer to the Address Map (PCH Platform Architecture
Specification) for further details on decoding.
Notes:
1. Setting the memory limit less than memory base disables the 32-bit memory
range altogether.
2. In general the memory base and limit registers will not be programmed by
software without clearing the MSE bit first.
3:0 RV 0h Reserved