Datasheet

Processor Uncore Configuration Registers
558 Datasheet, Volume 2
4.8.20 QPIREUT_PM_R0—REUT Power Management Register 0
QPIREUT_PM_R0
Bus: 1 Device: 8 Function: 3 Offset: 190h
Bus: 1 Device: 9 Function: 3 Offset: 190h
Bit Attr
Reset
Value
Description
31:28 RWS-LV 0b TL0sDriveRemote
27:26 RV 0b Reserved
25:24 RWS-LV 0b
TL0sSleepMinRemote: TL0S_SLEEP_MIN_REMOTE
If # of links supported is greater than 0 then, Link Select must always be used to
display the current read value for this field.
There is a write dependency for this field based on the value of Can Control
Multiple Links?
If Can Control Multiple Links? = 0, then Link Select must be used to only write to
the selected Link.
If Can Control Multiple Links? = 1, then every Link selected in Link Control will
receive the written value.
Intel QPI Behavior
TL0sSleepMinRemote and TL0sWakeRemote values are captured from TS
sequence and updated in this CSR. Software or BIOS can update these values as a
work-around.
It means software or BIOS will overwrite whatever values are captured from TS
sequence. On subsequent entry to InbandReset causes these values to be
overwritten again by hardware with values captured from TS sequence. To make
software or BIOS workaround permanent we need another control bit to tell
hardware not to update this CSR any more.
This field is decoded in the following way.
00 = 32UI
01 = 48 UI
10 = 64UI
11 = 96UI
Hardware loads this CSR with captured values from TS sequence if bit 15 is not
set.
Software or BIOS can always write to these CSRs. Whenever software or BIOS is
writes to this CSR, it also need to set bit 15 to make these values permanent.
TL0s_ignore_remote_values (bit 15)
When this bit is set, hardware ignores values received in TS sequence and uses
values programmed by software or BIOS.
23:22 RV 0b Reserved