Datasheet

Datasheet, Volume 2 557
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Processor Uncore Configuration Registers
4.8.19 DDRIOCompCfgSPDA[0:1] Register
Note: Only channel 1 or channel 3 are connected to the SPD buffers. Programming the A0
(channel 0 or channel2) has no effect.
SPD Comp Config and LVDDR enable, statically configured by BIOS and this is not part
of the period RCOMP.
DDRIOCompCfgSPDA[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 420h
Bus: 1 Device: 15 Function: 6 Offset: 420h
Bit Attr
Reset
Value
Description
31:28 RV 0h Reserved
27 RW-LB 0b
DDRIOBLOCKCOMPUPDATE
1b: Block all COMP update to CSR, to make sure msg channel update will not
conflict with comp update.
0b: Not blocked
EV software usage: need to set this bit prior issuing a configuration read access to
the RCOMP registers. This bit must be cleared after the RCOMP read; otherwise,
RCOMP is not updated
Only the DDRIOCOMPCFGSPDA1.DDRIOBLOCKCOMPUPDATE need to be updated.
The odd channel register is controlling both channels in each channel-pair.
Updating DDRIOCOMPCFGSPDA0.DDRIOBLOCKCOMPUPDATE has no effect.
26 RV 0b Reserved
25 RW-LB 0b
DDRIODebugSel
Select bit 3-2 from GDDebugMuxExtOut when bit is 1
24 RW-LB 0b
SPD_Viewdig_en
SPD ViewDig enable
23 RW-LB 0h
Comp_LVDDR_en
1.35 V LVDDR3 (DDR3L) enable when set
22 RW-LB 0b
SPD_ddr_chdbg_sel
Debug mux select in spd,
1’b1 - select ch0
21 RW-LB 0b
SPD_Slowbuffer_ctl2
Slow Buffer Control,
control ddr_viewdig0
20 RW-LB 0b
SPD_Slowbuffer_ctl1
Slow buffer control
Control ddr_viewdig1
19:15 RW-LB 00h
SPD_scomppctl
SPD SComp P-Control
14:10 RW-LB 0h
SPD_Scompnctl
SPD SComp N-Control
9:5 RW-LB 0h
SPD_rcomppctl
SPD RComp P-Control
4:0 RW-LB 00h
SPD_rcompnctl
SPD RComp N-Control