Datasheet

Processor Uncore Configuration Registers
556 Datasheet, Volume 2
4.8.18 DDRIOCompOVR5A[0:1] Register
TCO evaluation
5:3 RW-LB 100b
OFSTMirror_CR_drvcmdl1
CMD DRV UP offset value
2:0 RW-LB 100b
OFSTMirror_CR_drvcmd0
CMD DRV Down offset value
DDRIOCompOvrOfst2A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 41Ch
Bus: 1 Device: 15 Function: 6 Offset: 41Ch
Bit Attr
Reset
Value
Description
DDRIOCompOVR5A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 414h
Bus: 1 Device: 15 Function: 6 Offset: 414h
Bit Attr
Reset
Value
Description
31:14 RV 0 Reserved
13 RW-LB 0h
GDCPerChanCompCR: Comp Repeat Per Channel
Enable this bit to have the Comp process run twice, (one for each channel) every
iteration uses the channel specific ovr/ofst value.
The COMP FSM uses on MCIOCOMP_CH0 setting of this field and ignores
MCIOCOMP_CH1 field settings. Meaning:
Ch1 Ch0 compperchannel
0 0 no
0 1 yes
1 0 no
1 1 yes
Note: The logic in MC for MC2GDCompUpdate is the AND of both
GD2MCCompComplete from DDR01 and DD23. But when gdcperchancompcr is set
differently in CH0 and CH2, the GD2MCCompComplet pulses come at different
times from DDR01 and DDR23 so that the AND result is MC will not assert
MC2GDCompUpdate. Thus, the code will not be updated to the register which
controls the buffer in DDR. In order to have CompUpdate, software need to do the
following:
set both imc_c0_DDRIOcompovr5a0.gdcperchancompcr=1 &
imc_c2_DDRIOcompovr5a0.gdcperchancompcr=1
12:8 RW-LB 04h
GDCCmdSegEn4CompCR
How many segments will be open when evaluating CMD/CTL RCOMP.. For this
field, only the values from the Ch0 CR are taken.
7RW-LB0b
OVSel_CR_tco_evalOVR
TCO evaluation override select
6RW-LB0b
OVSel_CR_tco_directOVR
TCO direct override select
5:0 RW-LB 00h
OVRMirror_CR_tco
TCO override value