Datasheet

Datasheet, Volume 2 555
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Processor Uncore Configuration Registers
4.8.16 DDRIOCkLogicDelayA[0:1]—DDRIOCkLogicDelay Register
Logic delay of 1 QCLK in CLK slice
4.8.17 DDRIOCompOvrOfst2A[0:1]—
DDRIOCompOvrOfst2 Register
DDRIOCkLogicDelayA[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 398h
Bus: 1 Device: 15 Function: 6 Offset: 398h
Bit Attr
Reset
Value
Description
7:6 RV 0 Reserved
5:4 RW-LB 00b
DDRIOCKAlignLogicDelay1
Shifts Clock by one qclk.
For Ch01:
Bit 4 for Logic Delay Control for CK0/CK0#,
Bit 5 for Logic Delay Control for CK3/CK3#,
For Ch23:
Bit 4 for Logic Delay Control for CK3/CK3#,
Bit 5 for Logic Delay Control for CK0/CK0#
Applicable both in PI mode and in bypass mode
3:2 RV 0 Reserved
1:0 RW-LB 00b
DDRIOCKAlignLogicDelay0
Shifts Clock by one qclk.
For Ch01:
Bit 0 for Logic Delay Control for CK1/CK1#,
Bit 1 for Logic Delay Control for CK2/CK2#,
For Ch23:
Bit 0 for Logic Delay Control for CK2/CK2#,
Bit 1 for Logic Delay Control for,CK1/CK1#
Applicable both in PI mode and in bypass mode
DDRIOCompOvrOfst2A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 41Ch
Bus: 1 Device: 15 Function: 6 Offset: 41Ch
Bit Attr
Reset
Value
Description
31 RV 0b Reserved
30:28 RW-LB 100b
DDRIOTCOVREFOFST
TCO Vref Offset
27 RW-LB 1b
OFSTMirror_CR_stlegen1
DQ/CLK Drv UP Static Leg
26 RW-LB 1b
OFSTMirror_CR_stlegen0
DQ/CLK Drv Down Static Leg
25:21 RW-LB 07h
OFSTMirror_CR_scomp_cmdctl1
CMD Scomp Offset Value
20:16 RW-LB 0Bh
OFSTMirror_CR_scomp_cmdctl0
CTL Scomp Offset Value
15:11 RW-LB 18h
OFSTMirror_CR_scomp_dqclk1
DQ Scomp Offset Value
10:6 RW-LB dh
OFSTMirror_CR_scomp_dqclk0
CLK Scomp Offset Value