Datasheet

Processor Uncore Configuration Registers
554 Datasheet, Volume 2
4.8.15 DDRIOCkPiCode1A[0:1]—DDRIOCkPiCode1 Register
Defines PI coding for DDR CK pins:
Ch01: for CK0/CK0# and CK3/CK3#
Ch23: for CK3/CK3# and CK0/CK0#
DDRIOCkPiCode1A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 394h
Bus: 1 Device: 15 Function: 6 Offset: 394h
Bit Attr
Reset
Value
Description
31:26 RV 0 Reserved
25:24 RW-LB 11b
DDRIOCkXoverEnable1: CLK Xover Enable
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay.
Recommended to keep CLK, CMD and CTL together
For Ch01:
Bit 24 controls the clock xover enables for the CK0/CK0#
Bit 25 controls the clock xover enables for the CK3/CK3#
For Ch23:
Bit 24 controls the clock xover enables for the CK3/CK3#
Bit 25 controls the clock xover enables for the CK0/CK0#
23:14 RV 0 Reserved
13:8 RW-LB 0h
DDRIOCkPiCodeRank3
For Ch01, PI code for CK3/CK3#
For Ch23, PI code for CK0/CK0#
000000 = min delay
000001 = min + 1/64 qclk
...
111111 = min + 63/64 qclk
7:6 RV 0 Reserved
5:0 RW-LB 0h
DDRIOCkPiCodeRank1
For Ch01, PI code for CK0/CK0#
For Ch23, PI code for CK3/CK3#
000000 = min delay
000001 = min + 1/64 qclk
...
111111 = min + 63/64 qclk