Datasheet

Datasheet, Volume 2 553
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Processor Uncore Configuration Registers
4.8.14 DDRIOCkPiCode0A[0:1]—DDRIOCkPiCode0 Register
Defines PI coding for DDR CK pins:
Ch01: for CK1/CK1# and CK2/CK2#
Ch23: for CK2/CK2# and CK1/CK1#
DDRIOCkPiCode0A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 390h
Bus: 1 Device: 15 Function: 6 Offset: 390h
Bit Attr
Reset
Value
Description
31:26 RV 0 Reserved
25:24 RW-LB 11b
DDRIOCkXoverEnable0: CLK Xover Enable
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay.
Recommended to keep CLK, CMD and CTL together
For Ch01:
Bit 24 controls the clock xover enables for the CK1/CK1#
Bit 25 controls the clock xover enables for the CK2/CK2#
For Ch23:
Bit 24 controls the clock xover enables for the CK2/CK2#
Bit 25 controls the clock xover enables for the CK1/CK1#
23:14 RV 0 Reserved
13:8 RW-LB 0h
DDRIOCkPicodeRank2
For Ch01, PI code for CK2/CK2#
For Ch23, PI code for CK1/CK1#
000000 = min delay
000001 = min + 1/64 qclk
...
111111 = min + 63/64 qclk
7:6 RV 0 Reserved
5:0 RW-LB 0h
DDRIOCkPiCodeRank0
For Ch01, PI code for CK1/CK1#
For Ch23, PI code for CK2/CK2#
000000 = min delay
000001 = min + 1/64 qclk
...
111111 = min + 63/64 qclk