Datasheet

Processor Uncore Configuration Registers
550 Datasheet, Volume 2
4.8.10 DDRIOLogicDelayA[0:1]—DDRIOLogicDelay Register
Logic delay control register. When set, the corresponding PI group is delayed by one
qclk.
The LogicDelay register settings are additive delays to either the PhaseDelay setting or
the CMD/CTL PI settings, depending on the CmdXoverEnable setting.
4.8.11 DDRIOCtlRankCnfgA[0:1]—DDRIOCtlRankCnfg Register
DDRIOLogicDelayA[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 318h
Bus: 1 Device: 15 Function: 6 Offset: 318h
Bit Attr
Reset
Value
Description
31:12 RV 0b Reserved
11 RW-LB 0h CMDLogicDelay3: CMD Logic Delay for PI Group 3
10 RW-LB 0h CMDLogicDelay2: CMD Logic Delay for PI Group 2
9RW-LB0hCMDLogicDelay1: CMD Logic Delay for PI Group 1
8RW-LB0hCMDLogicDelay0: CMD Logic Delay for PI Group 0
7RV0bReserved
6RW-LB0hCTLLogicDelay6: CTL Logic Delay for PI Group 6
5RW-LB0hCTLLogicDelay5: CTL Logic Delay for PI Group 5
4RW-LB0hCTLLogicDelay4: CTL Logic Delay for PI Group 4
3RW-LB0hCTLLogicDelay3: CTL Logic Delay for PI Group 3
2RW-LB0hCTLLogicDelay2: CTL Logic Delay for PI Group 2
1RW-LB0hCTLLogicDelay1: CTL Logic Delay for PI Group 1
0RW-LB0hCTLLogicDelay0: CTL Logic Delay for PI Group 0
DDRIOCtlRankCnfgA[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 328h
Bus: 1 Device: 15 Function: 6 Offset: 328h
Bit Attr
Reset
Value
Description
15:12 RV 0b Reserved
11 RW-LB 1b
DDRIOEnRDIMM: RDIMM Enable
Setting this bit will decrease the command drive strength (for RDIMM).
9:8 RW-LB 11b DDRIOCtlD2RankCfg: DIMM2 Rank[1:0] CMD/CTL Enable
7:4 RW-LB Fh DDRIOCtlD1RankCfg: DIMM1 Rank[3:0] CMD/CTL Enable
3:0 RW-LB Fh DDRIOCtlD0RankCfg: DIMM0 Rank[3:0] CMD/CTL Enable