Datasheet

Datasheet, Volume 2 55
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.17 SECSTS—Secondary Status Register
SECSTS
Bus: 0 Device: 0 Function: 0 Offset: 1Eh (PCIe MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 1Eh
Bus: 0 Device: 2 Function: 0–3 Offset: 1Eh
Bus: 0 Device: 3 Function: 0–3 Offset: 1Eh
Bit Attr
Reset
Value
Description
15 RW1C 0b
Detected Parity Error
This bit is set by the root port when it receives a poisoned TLP in the PCI Express
port. This bit is set regardless of the state the Parity Error Response Enable bit in
the Bridge Control register.
14 RW1C 0b
Received System Error
This bit is set by the root port when it receives a ERR_FATAL or ERR_NONFATAL
message from PCI Express. This does not include the virtual ERR* messages that
are internally generated from the root port when it detects an error on its own.
13 RW1C 0b
Received Master Abort Status
This bit is set when the root port receives a Completion with Unsupported Request
Completion Status or when the root port master aborts a Type 0 configuration
packet that has a non-zero device number.
12 RW1C 0b
Received Target Abort Status
This bit is set when the root port receives a Completion with Completer Abort
Status.
11 RW1C 0b
Signaled Target Abort
This bit is set when the root port sends a completion packet with a Completer
Abort Status (including peer-to-peer completions that are forwarded from one
port to another).
10:9 RO 00b
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
8RW1C0b
Master Data Parity Error
This bit is set by the root port on the secondary side (PCI Express link) if the Parity
Error Response Enable bit (PERRE) is set in Bridge Control register and either of
the following two conditions occurs:
• The PCI Express port receives a Completion from PCI Express marked
poisoned.
• The PCI Express port poisons an outgoing packet with data.
If the Parity Error Response Enable bit in Bridge Control Register is cleared, this
bit is never set.
7RO 0b
Fast Back-to-Back Transactions Capable
Not applicable to PCI Express. Hardwired to 0.
6RV0hReserved
5RO 0b
PCI bus 66 MHz capability
Not applicable to PCI Express. Hardwired to 0.
4:0 RV 0h Reserved