Datasheet

Datasheet, Volume 2 549
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Processor Uncore Configuration Registers
4.8.9 DDRIOCtlPICode1A[0:1]—DDRIOCtlPICode1 Register
DDRIOCtlPICode1A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 314h
Bus: 1 Device: 15 Function: 6 Offset: 314h
Bit Attr
Reset
Value
Description
31:23 RV 0b Reserved
22 RW-LB 1b
DDRIO1CtlXoverEnable6: Xover Enable for CTL PI Group 6
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay
21:16 RW-LB 00h
DDRIO1CtlPiCode6: PI Code for CTL PI Group 6
000000 = min delay + offset delay
000001 = min delay + offset delay + 1/64 qclk
...
111111 = min delay + offset delay + 63/64 qclk
15 RV 0b Reserved
14 RW-LB 1b
DDRIO1CtlXoverEnable5: Xover Enable for CTL PI Group 5
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay
13:8 RW-LB 00h
DDRIO1CtlPiCode5: PI Code for CTL PI Group 5
000000 = min delay + offset delay
000001 = min delay + offset delay + 1/64 qclk
...
111111 = min delay + offset delay + 63/64 qclk
7RV0bReserved
6RW-LB 1b
DDRIO1CtlXoverEnable4: Xover Enable for CTL PI Group 4
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay
5:0 RW-LB 00h
DDRIO1CtlPiCode4: PI Code for CTL PI Group 4
000000 = min delay + offset delay
000001 = min delay + offset delay + 1/64 qclk
...
111111 = min delay + offset delay + 63/64 qclk