Datasheet

Processor Uncore Configuration Registers
548 Datasheet, Volume 2
4.8.8 DDRIOCtlPICode0A[0:1]—DDRIOCtlPICode0 Register
DDRIOCtlPICode0A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 310h
Bus: 1 Device: 15 Function: 6 Offset: 310h
Bit Attr
Reset
Value
Description
31 RV 0b Reserved
30 RW-LB 1b
DDRIO0CtlXoverEnable3: Xover Enable for PI Group 3
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay.
29:24 RW-LB 00h
DDRIO0CtlPiCode3
PI Coding for PI Group 3
000000 = min delay
000001 = min + 1/64 qclk
...
111111 = min + 63/64 qclk
23 RV 0b Reserved
22 RW-LB 1b
DDRIO0CtlXoverEnable2: Xover Enable for PI Group 2
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay.
21:16 RW-LB 00h
DDRIO0CtlPiCode2: PI Coding for PI Group 2
000000 = min delay
000001 = min + 1/64 qclk
...
111111 = min + 63/64 qclk
15 RV 0b Reserved
14 RW-LB 1b
DDRIO0CtlXoverEnable1: Xover Enable for PI Group 1
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay
13:8 RW-LB 00h
DDRIO0CtlPiCode1: PI Coding for PI Group 1
000000 = min delay
000001 = min + 1/64 qclk
...
111111 = min + 63/64 qclk
7RV0bReserved
6RW-LB1b
DDRIO0CtlXoverEnable0: Xover Enable for PI Group 1
When set, the phase interpolator is used. When cleared, the phase interpolator is
bypassed and delay is shorter than PI setting 0 due to PI intrinsic delay
5:0 RW-LB 00h
DDRIO0CtlPiCode0: PI Code for PI Group 0
000000 = min delay
000001 = min + 1/64 qclk
...
111111 = min + 63/64 qclk