Datasheet
Datasheet, Volume 2 547
Processor Uncore Configuration Registers
4.8.6 DDRIORXTopRank0A[0:1]—DDRIORXTopRank0 Register
4.8.7 DDRIOTXTopRank0A[0:1]—DDRIOTXTopRank0 Register
DDRIORXTopRank0A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 140h
Bus: 1 Device: 15 Function: 6 Offset: 140h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RW-LB 0h
DDRIORxRcvEnCodingN1
Defines the number of steps to delay ReceiveEnable (0-63), per rank setting.
Resolution CycleTime/64
23 RV 0h Reserved
22:16 RW-LB 0h
DDRIORxDqsNCodingN1
Defines the number of steps to delay DQSN on the receive path relative to DQ, per
rank setting. Resolution CycleTime/64
The range for DQSN/DQSP 7-bit codes is from 0b to 1001111b (0h to 4Fh, or 0h
to 79h).
15:14 RV 0h Reserved
13:8 RW-LB 0h
DDRIORxRcvEnCodingN0
Defines the number of steps to delay ReceiveEnable (0-63), per rank setting.
Resolution CycleTime/64
7RV0hReserved
6:0 RW-LB 0h
DDRIORxDqsPCodingN1
Defines the number of steps to delay DQSP on the receive path relative to DQ, per
rank setting. Resolution CycleTime/64
The valid range for DQSN/DQSP 7-bit codes is from 0b to 1001111b (0h to 4Fh, or
0h to 79h).
DDRIOTXTopRank0A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 160h
Bus: 1 Device: 15 Function: 6 Offset: 160h
Bit Attr
Reset
Value
Description
31:30 RV 0h Reserved
29:24 RW-LB 00h
DDRIOTxDqsCodingN1
Defines the number of steps to delay DQS (0-63) on the transmit path relative to
QCLK. Nibble 1 setting Resolution CycleTime/64
23:22 RV 0h Reserved
21:16 RW-LB 00h
DDRIOTxDqCodingN1
Defines the number of steps to delay DQ (0-63) on the transmit path relative to
QCLK, Nibble 0 setting. Resolution CycleTime/64, In case of overflow relative to
DQS use DDRIOTxDqDelayCycle to add an additional cycle delay
15:14 RV 0h Reserved
13:8 RW-LB 00h
DDRIOTxDqsCodingN0
Defines the number of steps to delay DQS (0-63) on the transmit path relative to
QCLK. Nibble 1 setting Resolution CycleTime/64
7:6 RV 0h Reserved
5:0 RW-LB 00h
DDRIOTxDqCodingN0
Defines the number of steps to delay DQ (0-63) on the transmit path relative to
QCLK , Nibble 0 setting. Resolution CycleTime/64, In case of overflow relative to
DQS use DDRIOTxDqDelayCycle to add an additional cycle delay