Datasheet

Processor Uncore Configuration Registers
546 Datasheet, Volume 2
4.8.5 DDRIOTXRXBotRank0A[0:1]—
DDRIOTXRXBotRank0 Register
DDRIOTXRXBotRank0A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 120h
Bus: 1 Device: 15 Function: 6 Offset: 120h
Bit Attr
Reset
Value
Description
31 RW-LB 0b
DDRIOTxDqDelayCycleN1
Determines the cycle delay between DQ and DQS before applying the PI settings.
Need to be used when DQS PI is bigger the DQ PI setting. This bit is for Nibble 1
30:28 RW-LB 000b
DDRIOTxDqsOutputEnableDelayN1
Defines the number of cycles(1-8) to delay the write transaction for Nibble 1
27 RW-LB 0b
DDRIOTxDqDelayCycleN0
Determines the cycle delay between DQ and DQS before applying the PI settings.
Need to be used when DQS PI is bigger the DQ PI setting. This bit is for Nibble 0
26:24 RW-LB 000b
DDRIOTxDqsOutputEnableDelayN0
Defines the number of cycles(1-8) to delay the write transaction for Nibble 0
23 RV 0h Reserved
22:16 RW-LB 0h
DDRIORxDqsNCodingN0
Defines the number of steps to delay DQSN (0-63) on the receive path relative to
DQ, per rank setting. Resolution CycleTime/64
15 RV 0h Reserved
14:12 RW-LB 000b
DDRIORxRcvEnLogicDelayN1
RX RcvEnable Logic Delay for nibble 1 - Fly By Adjustment, controls the cycle
offset between iMC indication of ReceiveEnable to input buffer opening, effective
range: 0-7 for 0-3.5 DCLKs.
11 RV 0h Reserved
10:8 RW-LB 000b
DDRIORxRcvEnLogicDelayN0
RX RcvEnable Logic Delay for nibble 0 – Fly By Adjustment, controls the cycle
offset between iMC indication of ReceiveEnable to input buffer opening, effective
range: 0-7 for 0-3.5 DCLKs.
7RV0hReserved
6:0 RW-LB 0h
DDRIORxDQqsPCodingN0
Defines the number of steps to delay DQSP (0-63) on the receive path relative to
DQ, per rank setting. Resolution CycleTime/64