Datasheet

Processor Uncore Configuration Registers
544 Datasheet, Volume 2
4.8.2 DDRIOTrainingResult1A[0:1]—
DDRIOTrainingResult1 Register
4.8.3 DDRIOTrainingResult2A[0:1]—
DDRIOTrainingResult2 Register
1RW-LB0b
DDRIOWriteLevelingTrainEnable
Write Leveling training mode enable. In this mode a programmable # of DQS
pulses are issued according to EnableDqsWL setup. The DDR (which should also
be in WR-leveling mode) samples CLK with DQS rising edge and drives it on one of
the DQ pins. In this mode only WR command sends strobe. In order to sample the
DQ pins, a RD command should be sent. In this mode the RD command will not be
issued on command and DQS pins, but DQ is sampled, OR’ed for the whole byte
and result is loaded into training-result register, into the bit pointed by WR-
leveling PI setting.
Note: In the end of WR-leveling operation MCIO reset should be issued
0RW-LB0b
DDRIOReceiveEnableTrainEnable
This bit indicates Receive Enable training mode. In this mode the DQS is sampled
by the RCV-EN, and loaded into training-result register pair according to the
receive-enable PI setting. After exiting this mode, MCIO reset is required.
DDRIOTrainingResult1A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 10Ch
Bus: 1 Device: 15 Function: 6 Offset: 10Ch
Bit Attr
Reset
Value
Description
31:0 RW-LB
000000
00h
DataInTrainingRes1CR
Training results bits 31:0
DDRIOTrainingResult2A[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 110h
Bus: 1 Device: 15 Function: 6 Offset: 110h
Bit Attr
Reset
Value
Description
31:0 RW-LB
000000
00h
DataInTrainingRes2CR
Training results bits 63:32
DDRIOTrainingModeA[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 108h
Bus: 1 Device: 15 Function: 6 Offset: 108h
Bit Attr
Reset
Value
Description