Datasheet

Datasheet, Volume 2 543
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Processor Uncore Configuration Registers
4.8 MISC Registers
4.8.1 DDRIOTrainingModeA[0:1]—DDRIOTrainingMode Register
DDRIOTrainingModeA[0:1]
Bus: 1 Device: 17 Function: 0 Offset: 108h
Bus: 1 Device: 15 Function: 6 Offset: 108h
Bit Attr
Reset
Value
Description
31:23 RV 0h Reserved
22 RW-LB 0b
DDRIOX4X8
Dynamic X4/X8 mode
21 RW-LB 0h
DDRIORDIMMEn
Tdqs enable, when enabled, in tdqs mode. Previously called rdimm_en
20 RW-LB 0b
DDRIOBL4
Enable Burst Length of 4 Mode; set by BIOS for BC4 mode after training exited
from IOSAV
19 RV 0h Reserved
18 RW-LB 0b
DDRIORxLongD0N1
Slave DLL N1
Delay READ DQ for 1/8 UI (QCLK)
17 RW-LB 0b
DDRIORxLongD0N0
Slave DLL N0
Delay READ DQ for 1/8 UI (QCLK)
14 RV 0h Reserved
11 RW-LB 0b
DDRIODqDqstraingingRes
In RX DqDqs training mode indicate write result from DIMM to CRTraining
Result.(not sure if it is needed)
Read DQ/DQS capture training result
10 RV 0h Reserved
9:6 RW-LB 0h
DDRIODqsEnableWL
Indicates which strobes to toggle during Write Leveling mode. decoding :
In WL training mode (trainmode bit 1 set to 1), MC sends NOP writes at regular
intervals in order to send isolated DQS pulses to the DIMM (the DIMM, in turn,
samples the clock with DQS and returns the result through the DQ prime bit). To
select how many DQS pulses are sent out at each NOP write, set bit 6 to 0 and set
bits 9:7 to a non-zero value. To send 3 contiguous DQS pulses, set bits 9:7 to 111.
To send only one DQS pulse, set bits 9:7 to 001, 010, or 100. To send 2
contiguous DQS pulses, set bits 9:7 to 011 or 110. To send a sequence of 1 DQS
pulse followed immediately by 1 dead cycle, followed immediately by another DQS
pulse, set bits 9:7 to 101.
Bit #6 can be set to 1, in which case DQS will be toggling continuously during WL
training mode, except when MC sends a NOP write, at which point DQS will toggle
according to bits 9:7 as described above. If one is to set bit 6 to 1, make sure that
at least one of bits 9:7 is set to 0, so that DQS PI code updates are issued every
time MC sends a NOP write (otherwise, DQS timing will remain the same no
matter what PI codes are programmed into the CR).
5:2 RW-LB 0h
DDRIOtrainRank
Training Rank (logical rank) Selection
bit 5 = reserved
bit 4–2 = logical rank
During both training (IOSAV) and NORMAL modes, PI setting going to DLL and I/O
logic is always decided by the mc2gdread/writerank[2:0] signals. But during
training (IOSAV) mode, DDRIOtrainRank indirectly selects which PI setting is
relevant in the current training stage. The relevant PI setting is the one that
controls which result register you’re writing to.