Datasheet

Processor Uncore Configuration Registers
542 Datasheet, Volume 2
4.7.1.14 R2PCIE_ASC_LDVAL Register
4.7.1.15 R2PCIE_ASC_CONTROL Register
4.7.1.16 R2PCIE_GLB_RSP_CNTRL Register
4.7.1.17 R2PCIE_LCL_RESP_CNTRL Register
R2PCIE_ASC_LDVAL
Bus: 1 Device: 19 Function: 0 Offset: ECh
Bit Attr
Reset
Value
Description
31:16 RWS-L 0000h load_high_value
15:0 RWS-L 0000h load_low_value
R2PCIE_ASC_CONTROL
Bus: 1 Device: 19 Function: 0 Offset: F0h
Bit Attr
Reset
Value
Description
15:11 RV 0h Reserved
10:8 RWS-L 0h mbp_selector
7RWS-L0benable_mbp_qualification
6:2 RV 0h Reserved
1RWS-L0benable_asc0
0RWS-LV0bcurrent_asc0_state_output
R2PCIE_GLB_RSP_CNTRL
Bus: 1 Device: 19 Function: 0 Offset: F2h
Bit Attr
Reset
Value
Description
15:14 RV 0h Reserved
13:11 RWS-L 000b stop_trigger_selector_for_global_response_1
10:8 RWS-L 000b start_trigger_selector_for_global_response_1
7:6 RV 0h Reserved
5:3 RWS-L 000b stop_trigger_selector_for_global_response_0
2:0 RWS-L 000b start_trigger_selector_for_global_response_0
R2PCIE_LCL_RESP_CNTRL
Bus: 1 Device: 19 Function: 0 Offset: F4h
Bit Attr
Reset
Value
Description
15:0 RW 0000h Reserved