Datasheet

Processor Integrated I/O (IIO) Configuration Registers
54 Datasheet, Volume 2
3.2.4.15 IOBAS—I/O Base Register
3.2.4.16 IOLIM—I/O Limit Register
IOBAS
Bus: 0 Device: 0 Function: 0 Offset: 1Ch (PCIe MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 1Ch
Bus: 0 Device: 2 Function: 0–3 Offset: 1Ch
Bus: 0 Device: 3 Function: 0–3 Offset: 1Ch
Bit Attr
Reset
Value
Description
7:4 RW Fh
I/O Base Address
This field corresponds to A[15:12] of the I/O base address of the PCI Express
port. See also the IOLIM register description.
3:2 RW-L 3h
More I/O Base Address
When EN1K is set in the Section 3.3.4, “Global System Control and Error
Registers” on page 191 register, these bits become RW and allow for 1K
granularity of I/O addressing; otherwise, these are RO.
1:0 RO 0h
I/O Address capability
IIO supports only 16 bit addressing.
IOLIM
Bus: 0 Device: 0 Function: 0 Offset: 1Dh (PCIe MODE)
Bus: 0 Device: 1 Function: 0–1 Offset: 1Dh
Bus: 0 Device: 2 Function: 0–3 Offset: 1Dh
Bus: 0 Device: 3 Function: 0–3 Offset: 1Dh
Bit Attr
Reset
Value
Description
7:4 RW 0h
I/O Address Limit
This field corresponds to A[15:12] of the I/O limit address of the PCI Express port.
The I/O Base and I/O Limit registers define an address range that is used by the
PCI Express port to determine when to forward I/O transactions from one
interface to the other using the following formula:
IO_BASE  A[15:12]  IO_LIMIT
The bottom of the defined I/O address range will be aligned to a 4 KB boundary
(1 KB if EN1K bit is set. Refer to Section 3.3.4, “Global System Control and Error
Registers” on page 191 for definition of EN1K bit) while the top of the region
specified by IO_LIMIT will be one less than a 4 KB (1 KB if EN1K bit is set)
multiple.
Notes:
1. Setting the I/O limit less than I/O base disables the I/O range altogether.
2. In general the I/O base and limit registers will not be programmed by
software without clearing the IOSE bit first.
3:2 RW-L 0h
More I/O Address Limit
When EN1K is set in Section 3.3.4, “Global System Control and Error Registers”
register, these bits become RW and allow for 1K granularity of I/O addressing,
otherwise these are RO.
1:0 RO 0h
I/O Address Limit Capability
IIO only supports 16 bit addressing.