Datasheet

Datasheet, Volume 2 539
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Processor Uncore Configuration Registers
4.7.1.8 R2EGRERRLOG Register
R2EGRERRLOG
Bus: 1 Device: 19 Function: 0 Offset: B0h
Bit Attr
Reset
Value
Description
31:26 RV 0h Reserved
25 RW1CS 0b CBo7 Credit Overflow
24 RW1CS 0b CBo6 Credit Overflow
23 RW1CS 0b CBo5 Credit Overflow
22 RW1CS 0b CBo4 Credit Overflow
21 RW1CS 0b CBo3 Credit Overflow
20 RW1CS 0b CBo2 Credit Overflow
19 RW1CS 0b CBo1 Credit Overflow
18 RW1CS 0b CBo0 Credit Overflow
17 RW1CS 0b ADEgress1_Overflow
16 RW1CS 0b ADEgress0_Overflow
15 RW1CS 0b BLEgress1_Overflow
14 RW1CS 0b BLEgress0_Overflow
13 RW1CS 0b AKEgress_Overflow
12 RW1CS 0b ADEgress1_Write_to_Valid_Entry
11 RW1CS 0b ADEgress0_Write_to_Valid_Entry
10 RW1CS 0b BLEgress1_Write_to_Valid_Entry
9RW1CS 0bBLEgress0_Write_to_Valid_Entry
8RW1CS 0bAKEgress_Write_to_Valid_Entry
7RW1CS 0bCbo7VfifoCrdOverflow
6RW1CS 0bCbo6VfifoCrdOverflow
5RW1CS 0bCbo5VfifoCrdOverflow
4RW1CS 0bCbo4VfifoCrdOverflow
3RW1CS 0bCbo3VfifoCrdOverflow
2RW1CS 0bCbo2VfifoCrdOverflow
1RW1CS 0bCbo1VfifoCrdOverflow
0RW1CS 0bCbo0VfifoCrdOverflow