Datasheet

Processor Uncore Configuration Registers
532 Datasheet, Volume 2
4.6.2.6 PmonUnitStatus—Performance Unit Status Register
This field shows which registers have overflowed in the unit.
Whenever a register overflows, it should set the relevant bit to 1. An overflow should
not effect the other status bits. This status should only be cleared by software.
Seven bits for this status have been defined. This is overkill for many units. See below
for the bits that are used in the different units.
In general, if the unit has a fixed counter, it will use bit 0. Counter 0 would use the
next LSB, and the largest counter would use the MSB.
HA: [4:0] w/ [4] = Counter4 and [0] = Counter 0
iMC: [5:0] w/ [0] = Fixed; [1] = Counter0 and [5] = Counter4
PCU: [3:0]: [0] = Counter0 and [3] = Counter 3
IO IRP0: [0] = Counter0; [1] = Counter1
IO IRP1: [2] = Counter0; [3] = Counter1
0WO 0h
Reset Counter Configs
When this bit is written to, the counter configuration registers will be reset. This
does not effect the values in the counters. To reset the counters, this bit need
only be set by one of the unit control registers.
PmonUnitCtrll
Bus: 1 Device: 8 Function: 2 Offset: F4h
Bus: 1 Device: 9 Function: 2 Offset: F4h
Bus: 1 Device: 14 Function: 1 Offset: F4h
Bus: 1 Device: 16 Function: 0, 1,4,5 Offset: F4h
Bus: 1 Device: 19 Function: 1 Offset: F4h
Bit Attr
Reset
Value
Description
Unit Status
Bus: 1 Device: 8 Function: 2 Offset: F8h
Bus: 1 Device: 9 Function: 2 Offset: F8h
Bus: 1 Device: 14 Function: 1 Offset: F8h
Bus: 1 Device: 16 Function: 0,1,4,5 Offset: F8h
Bus: 1 Device: 19 Function: 1 Offset: F8h
Bit Attr
Reset
Value
Description
31:7 RV 0h Reserved
6:0 RW1C 00h
Counter Overflow Bitmask
This is a bitmask that specifies which counter (or counters) have overflowed.
If the unit has a fixed counter, its corresponding bitmask will be stored at
position 0.