Datasheet

Datasheet, Volume 2 531

Processor Uncore Configuration Registers
4.6.2.5 PmonUnitCtrl—Performance Unit Control Register
16 WO 0h
Queue Occupancy Reset
This write only bit causes the queue occupancy counter of the PerfMon counter
for which this Perf event select register is associated to be cleared to all zeroes
when a 1 is written to it. No action is taken when a 0 is written.
Note: Since the queue occupancy counters never drop below zero, it is possible
for the counters to ’catch up’ with the real occupancy of the queue in question
when the real occupancy drop to zero.
15:8 RW-V 00h
Unit Mask
This mask selects the sub-events to be selected for creation of the event. The
selected sub-events are bitwise OR-ed together to create event. At least one
sub-event must be selected otherwise the PerfMon event signals will not ever
get asserted. Events with no sub-events listed effectively have only one sub-
event -- bit 8 must be set to 1 in this case.
7:0 RW-V 00h
Event Select
This field is used to decode the PerfMon event which is selected.
PmonUnitCtrll
Bus: 1 Device: 8 Function: 2 Offset: F4h
Bus: 1 Device: 9 Function: 2 Offset: F4h
Bus: 1 Device: 14 Function: 1 Offset: F4h
Bus: 1 Device: 16 Function: 0, 1,4,5 Offset: F4h
Bus: 1 Device: 19 Function: 1 Offset: F4h
Bit Attr
Reset
Value
Description
31:18 RV 0h Reserved
17 RW 0h
Overflow Enable
This bit controls the behavior of counters when they overflow. When set, the
system will trigger the overflow handling process throughout the rest of the
uncore, potentially triggering a PMI and freezing counters. When it is not set,
the counters will simply wrap around and continue to count. For overflow to be
enabled for a given unit, all of the unit control registers must have this bit set.
16 RW 0h
Freeze Enable
This bit controls what the counters in the unit will do when they receive a freeze
signal. When set, the counters will be allowed to freeze. When not set, the
counters will ignore the freeze signal. For freeze to be enabled for a given unit,
all of the unit control registers must have this bit set.
15:9 RV 0h Reserved
8RW-V 0h
Freeze Counters
This bit is written to when the counters should be frozen. If this bit is written to
and freeze is enabled, the counters in the unit will stop counting. To freeze the
counters, this bit need only be set by one of the unit control registers.
7:2 RV 0h Reserved
1WO 0h
Reset Counters
When this bit is written to, the counters data fields will be reset. The
configuration values will not be reset. To reset the counters, this bit need only be
set by one of the unit control registers.
PmonCntrCfg
Bus: 1 Device: 8 Function: 2 Offset: D8h, DCh, E0h, E4h, E8h
Bus: 1 Device: 9 Function: 2 Offset: D8h, DCh, E0h, E4h, E8h
Bus: 1 Device: 14 Function: 1 Offset: D8h, DCh, E0h, E4h, E8h
Bus: 1 Device: 16 Function: 0, 1,4,5 Offset: D8h, DCh, E0h, E4h, E8h
Bus: 1 Device: 19 Function: 1 Offset: D8h, DCh, E0h, E4h, E8h
Bit Attr
Reset
Value
Description