Datasheet

Processor Uncore Configuration Registers
526 Datasheet, Volume 2
4.5.3.5 DEVHIDE[0:7]—Device Hide 0 Register
Device Hide Register in CSR space
4.5.3.6 CPUBUSNO—CPU Bus Number Register
This register provides the Bus Number Configuration for the processor
4.5.3.7 SMICtrl—SMI Control Register
SMI generation control
DEVHIDE[0:7]
Bus: 1 Device: 11 Function: 3 Offset: B0h, B4h, B8h, BCh, C0h, C4h, C8h,
CCh
Bit Attr
Reset
Value
Description
31:0 RW-LB
000000
00h
Disable Function: Disable Function(DisFn):
A bit set in this register implies that the appropriate device function is not
enabled. For example, if bit 5 is set in DEVHIDE4, then it means that in device 5,
function 4 is disabled.
CPUBUSNO
Bus: 1 Device: 11 Function: 3 Offset: D0h
Bit Attr
Reset
Value
Description
31 RW-LB 0b
Valid
Indicates whether the bus numbers have been initialized or not
30:16 RV 0h Reserved
15:8 RW-LB 00h
CPU Bus Number 1
Bus Number for non IIO devices in the uncore
7:0 RW-LB 00h
CPU Bus Number 0
Bus Number for IIO devices
SMICtrl
Bus: 1 Device: 11 Function: 3 Offset: D8h
Bit Attr
Reset
Value
Description
31:26 RV 0h Reserved
25 RW 0b
Disable Generation of Intel SMI
Disable generation of Intel SMI
24 RW 0b
UMC SMI Enable
This is the enable bit that enables Intel SMI generation due to a UMC.
1 = Generate SMI after the threshold counter expires.
0 = Disable generation of SMI
23:20 RV 0h Reserved
19:0 RW 00000h
SMI generation threshold
This is the countdown that happens in the hardware before an SMI is generated
due to a UMC