Datasheet

Processor Uncore Configuration Registers
522 Datasheet, Volume 2
4.5.2.6 CoreCount—Number of Cores Register
Reflection of the LTCount2 register
4.5.2.7 UBOXErrSts—Error Status Register
This is error status register in the UBOX and covers most of the interrupt related errors
CoreCount
Bus: 1 Device: 11 Function: 0 Offset: 60h
Bit Attr
Reset
Value
Description
31:5 RV 0h Reserved
4:0 RO-V 0h
Core Count
Reflection of the LTCount2 uCR
UBOXErrSts
Bus: 1 Device: 11 Function: 0 Offset: 64h
Bit Attr
Reset
Value
Description
31:7 RV 0h Reserved
6RWS0b
Unsupported Mask
Mask SMI generation on receiving unsupported opcodes.
5RWS0b
Poison Mask
Mask SMI generation on receiving poison in UBOX.
4RW-V 0b
Unsupported Opcode received by UBOX
Unsupported opcode received by UBOX
3RW-V 0b
Poison was received by UBOX
UBOX received a poisoned transaction
2RV0hReserved
1RW-V 0b
SMI source iMC
SMI is caused due to an indication from the iMC
0RW-V 0b
SMI is caused due to a locally generated UMC
This is a bit that indicates that an SMI was caused due to a locally generated UMC