Datasheet

Processor Uncore Configuration Registers
520 Datasheet, Volume 2
4.5.2.3 IntControl—Interrupt Control Register
Interrupt Configuration Register
IntControl
Bus: 1 Device: 11 Function: 0 Offset: 48h
Bit Attr
Reset
Value
Description
31:19 RV 0h Reserved
18 RW-LB 0b
IA32 Logical Flat or Cluster Mode Override Enable
0 = IA32 Logical Flat or Cluster Mode bit is locked as Read only bit.
1 = IA32 Logical Flat or Cluster Mode bit may be written by SW, values written by
xTPR update are ignored.
For one time override of the IA32 Logical Flat or Cluster Mode value, return this bit
to its default state after the bit is changed. Leaving this bit as 1 will prevent
automatic update of the filter.
17 RW-LBV 0b
IA32 Logical Flat or Cluster Mode
Set by BIOS to indicate if the OS is running logical flat or logical cluster mode.
This bit can also be updated by IntPrioUpd messages.
This bit reflects the setup of the filter at any given time.
0 = Flat
1 = Cluster
16 RW-LB 0b
Cluster Check Sampling Mode
0 = Disable checking for Logical_APICID[31:0] being non-zero when sampling
flat/ cluster mode bit in the IntPrioUpd message as part of setting bit 1 in this
register
1 = Enable the above checking
15:11 RV 0h Reserved
10:8 RW-LB 000b
Vecor Based Hashe Mode Control
This field indicates the hash mode control for the interrupt control.
Select the hush function for the Vector based Hash Mode interrupt redirection
control :
000 = Select bits 7:4/5:4 for vector cluster/flat algorithm
001 = Select bits 6:3/4:3
010 = Select bits 4:1/2:1
011 = Select bits 3:0/1:0
other = Reserved
7RV0hReserved
6:4 RW-LB 000b
Redirection Mode Select for Logical Interrupts
Selects the redirection mode used for MSI interrupts with lowest-priority delivery
mode. The following schemes are used :
000 = Fixed Priority - select the first enabled APIC in the cluster.
001 = Redirect last vector selected (applicable only in extended mode)
010 = Hash Vector - select the first enabled APIC in round robin manner starting
form the hash of the vector number.
default: Fixed Priority
3:2 RV 0h Reserved
1RW-LB0b
Force to X2 APIC Mode
Write:
1 = Forces the system to move into X2APIC Mode.
0 = No affect
Functional only if X2APIC mode is enabled using bit[0] of the same register.
0RW-LB0b
Extended APIC Enable
Set this bit if you would like extended XAPIC configuration to be used.
0b1 -> X2APIC is enabled in the system
0b0 -> X2APIC is disabled in the system
This is just a defeature bit and does not enable X2APIC mode.