Datasheet

Processor Integrated I/O (IIO) Configuration Registers
52 Datasheet, Volume 2
3.2.4.8 PLAT—Primary Latency Timer Register
3.2.4.9 HDR—Header Type Register
3.2.4.10 HDR—Header Type Register
PLAT
Bus: 0 Device: 0 Function: 0 Offset: 0Dh
Bus: 0 Device: 1 Function: 0–1 Offset: 0Dh
Bus: 0 Device: 2 Function: 0–3 Offset: 0Dh
Bus: 0 Device: 3 Function: 0–3 Offset: 0Dh
Bit Attr
Reset
Value
Description
7:0 RO 0h
Primary Latency Timer
Not applicable to PCI Express. Hardwired to 00h.
HDR
Bus: 0 Device: 0 Function: 0 Offset: 0Eh
Bit Attr
Reset
Value
Description
7RO0b
Multi-function Device
This bit defaults to 0 for Device 0.
6:0 RO-V 00h
Configuration Layout
This field identifies the format of the configuration header layout.
In DMI mode, default is 00h indicating a conventional type 00h PCI header.
HDR
Bus: 0 Device: 1 Function: 0–1 Offset: 0Eh
Bus: 0 Device: 2 Function: 0–3 Offset: 0Eh
Bus: 0 Device: 3 Function: 0–3 Offset: 0Eh
Bit Attr
Reset
Value
Description
7RO-V1b
Multi-function Device
This bit defaults to 1 for Devices 1–3 since these are multi-function devices.
BIOS can individually control the value of this bit in Function 0 of these devices,
based on the HDRTYPCTRL register. BIOS will write to that register to change this
field to 0 in Function 0 of these devices if it exposes only Function 0 in the device
to OS.
Note: In product SKUs where only Function 0 of the device is exposed to any
software (BIOS/OS), BIOS would still have to set the control bits mentioned above
to set the bit in this register to be compliant per PCI rules.
6:0 RO 01h
Configuration Layout
This field identifies the format of the configuration header layout. It is Type1 for all
PCI Express root ports. The default is 01h indicating a PCI to PCI Bridge.