Datasheet

Processor Uncore Configuration Registers
516 Datasheet, Volume 2
4.4.5.8 FLEX_RATIO—Flexible Ratio Register
This ’flexible boot’ register is written by BIOS in order to modify the maximum non-
turbo ratio on the next reset.
4.4.5.9 RESOLVED_CORES_MASK—Resolved Cores Mask Register
4.4.5.10 PWR_LIMIT_MISC_INFO Register
FLEX_RATIO
Bus: 1 Device: 10 Function: 3 Offset: A0h
Bit Attr
Reset
Value
Description
63:17 RV 0h Reserved
16 RWS 0b
Flex Enable
Flex Ratio Enabled
15:8 RWS 00h
Flex Ratio
Desired Flex ratio.
7:0 RWS 00h
Over Clocking Extra Voltage
Extra voltage to be used for Over Clocking. The voltage is defined in units of 1/256
Volts.
RESOLVED_CORES_MASK
Bus: 1 Device: 10 Function: 3 Offset: B0h
Bit Attr
Reset
Value
Description
31:25 RV 0h Reserved
24 RO-V 0b
SMT Capability
0 = 1 thread
1 = 2 threads
23:16 RO-V 0h
Fused Core Mask
Vector of fused enabled IA cores in the package.
15:10 RV 0h Reserved
9:8 RO-V 00b
Thread Mask
Thread Mask indicates which threads are enabled in the core. The LSB is the
enable bit for Thread 0, whereas the MSB is the enable bit for Thread 1.
7:0 RO-V 00h
Core Mask
The resolved IA core mask contains the functional and non-defeatured IA cores.
The mask is indexed by logical ID. It is normally contiguous, unless BIOS
defeature is activated on a particular core.
Ucode will read this mask in order to decide on BSP and APIC IDs.
PWR_LIMIT_MISC_INFO
Bus: N Device: 10 Function: 3 Offset: F8h
Bit Attr
Reset
Value
Description
31:22 RV 0h Reserved
21:15 RO-FW 00h
Minimal PBM Window Size
Minimal Time window
14:0 RO-FW 0000h
Socket Power at PN
Skt power at Pn