Datasheet

Datasheet, Volume 2 515
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Processor Uncore Configuration Registers
4.4.5.7 CAPID4 Register
This register is a Capability Register used to expose enable/disable Fuses to BIOS for
SKU differentiation.
12 RO-FW 0b
DISABLE_3N: Fused 3N Disable Control
When set, 3N mode under normal/IOSAV operation (excluding MRS) is disabled.
The default value may change after reset de-assertion.
11 RO-FW 0b
DISABLE_DIR
DIR disable control. When set, directory is disabled.
10 RO-FW 0b
DISABLE_ECC: ECC Disable Control
When set, ECC is disabled.
9RO-FW 0b
DISABLE_QR_DIMM: QR DIMM Disable Control
When set, CS signals for QR-DIMM in slot 0-1 is disabled. Note: some CS may
have multiplexed with address signal to support extended addressing. The CS
signal disabling is only applicable to CS not the being multiplexed with address.
The default value may change after reset de-assertion.
8RO-FW 0b
DISABLE_4GBIT_DDR3: 4Gb Disable Control
When set, the address decode to the corresponding 4Gb mapping is disabled.
Note: LR-DIMM’s logical device density is also limited to 4Gb when this fuse is set.
The default value may change after reset de-assertion.
7RO-FW 0b
DISABLE_8GBIT_DDR3: 8Gb or Higher Disable Control
When set, the address decode to the corresponding 8Gb or higher mapping is
disabled. The default value may change after reset de-assertion.
6RV0hReserved
5RO-FW 0b
DISABLE_3_DPC: 3 DPC Disable Control
When set, CS signals for DIMM slot 2 are disabled.
Note: Some CS may have multiplexed with address signal to support extended
addressing. The CS signal disabling is only applicable to CS not the being
multiplexed with address.
The default value may change after reset de-assertion.
4RO-FW 0b
DISABLE_2_DPC: 2 DPC Disable Control
When set, CS signals for DIMM slot 1-2 (that is, slots 0 is not disabled) are
disabled.
Note: some CS may have multiplexed with address signal to support extended
addressing. The CS signal disabling is only applicable to CS not the being
multiplexed with address.
The default value may change after reset de-assertion.
3:0 RO-FW 0h
CHN_DISABLE: Channel Disable Control
When set, the corresponding channel is disabled. The default value may change
after reset de-assertion.
CAPID3
Bus: 1 Device: 10 Function: 3 Offset: 90h
Bit Attr
Reset
Value
Description
CAPID4
Bus: 1 Device: 10 Function: 3 Offset: 94h
Bit Attr
Reset
Value
Description
31:0 RO-FW
000000
00h
Reserved