Datasheet

Processor Uncore Configuration Registers
514 Datasheet, Volume 2
4.4.5.6 CAPID3 Register
This register is a processor Capability Register used to expose to BIOS for SKU
differentiation.
CAPID3
Bus: 1 Device: 10 Function: 3 Offset: 90h
Bit Attr
Reset
Value
Description
31:30 RO-FW 00b MC_SPARE
29:24 RO-FW 0h
MC2GD: MC2GDBit[5:4]
Tx Pulse Width Control Bit[1:0].
00 = Reset Value
01 = Short
11 = Long
10 = Reserved
MC2GDBit3 = DLL VRM: Increase Resistance in the VRM Feedback loop
MC2GDBit2 = DLL VRM: Increase Amp Current in the VRM Feedback loop
MC2GDBit1 = DLL Startup Time setting. 1 = 16cycles, 0 = 32cycles
MC2GDBit0 = 1.35V DDR3L LVDDR disable
Download from PCU may change the default value after reset de-assertion.
23 RO-FW 0b
DISABLE MONROE TECHNOLOGY
Monroe Technology Disable
22 RO-FW 0b
DISABLE_SMBUS_WRT: RAID-On-LOAD Disable Control
SMBUS write capability disable control. When set, SMBus write is disabled.
21 RO-FW 0b
DISABLE_ROL_OR_ADR
When set, memory ignores ADR event.
20 RO-FW 0b
DISABLE_EXTENDED_ADDR_DIMM: Extended Addressing DIMM Disable
Control
When set, DIMM with extended addressing (MA[17/16] is forced to be zero when
driving MA[17:16]. The default value may change after reset de-assertion.
19 RO-FW 0b
DISABLE_EXTENDED_LATENCY_DIMM: Extended Latency DIMM Disable
Ccontrol
When set, DIMM with extended latency is forced to CAS to be less than or equal to
14. The default value may change after reset de-assertion.
18 RO-FW 0b
DISABLE_PATROL_SCRUB: Patrol Scrub Disable Control
When set, rank patrol scrub is disabled. The default value may change after reset
de-assertion.
17 RO-FW 0b
DISABLE_SPARING: Sparing Disable Control
When set, rank sparing is disabled. The default value may change after reset de-
assertion.
16 RO-FW 0b
DISABLE_LOCKSTEP: LOCKSTEP Disable Control
When set, channel lockstep operation is disabled by forcing independent channel
mode. The default value may change after reset de-assertion.
15 RO-FW 0b
DISABLE_CLTT: CLTT Disable Control
When set, CLTT support is disabled by disabling TSOD polling. The default value
may change after reset de-assertion.
14 RO-FW 0b
DISABLE_UDIMM: UDIMM Disable Control
When set, UDIMM support is disabled by disabling address bit swizzling. The
default value may change after reset de-assertion.
13 RO-FW 0b
DISABLE_RDIMM: RDIMM Disable Control
When set, RDIMM support is disabled by disabling the RDIMM control word access.
In addition, the upper 5 bits of the 13b T_STAB register will be treated as zeros;
that is, the T_STAB can only have max of 255 DCLK delay after clock-stopped
power down mode which is in sufficient for normal RDIMM clock stabilization;
hence, users will not be able to support self-refresh with clock off mode (S3, pkg
C6) if the RDIMM disable is one. The default value may change after reset de-
assertion.