Datasheet

Datasheet, Volume 2 513
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Processor Uncore Configuration Registers
4.4.5.5 CAPID2 Register
This register is a processor Capability Register used to expose to BIOS for SKU
differentiation.
CAPID2
Bus: 1 Device: 10 Function: 3 Offset: 8Ch
Bit Attr
Reset
Value
Description
31:30 RO-FW 00b QPI_SPARE
29:25 RO-FW 0h
QPI_ALLOWED_CFCLK_RATIO_DIS
Allowed CFCLK ratio is 12, 11, 10, 9, 8 (default), 7; one bit is allocated for each
supported ratio except 8, the default ratio. Intel QPI transfer rate = 8 * CFCLK.
Bits are organized as r12_r11_r10_r9_r7 format. 0/1 --> ratio supported/
not_supported. Reset Value ratio of 8 is always supported; hence cannot be
disabled. Ex:
00000 ==> Supported ratio: 12, 11, 10, 9, 8 (default), 7; ratio not supported:
none
00001 ==> Supported ratio: 12, 11, 10, 9, 8 (default); ratio not supported: 7
........
11111 ==> Supported ratio: 8 (default); ratio not supported: 12, 11, 10, 9, 7
24 RO-FW 0b
QPI_LINK1_DIS
When set Intel QPI link 1 will be disabled.
23 RO-FW 0b
QPI_LINK0_DIS
When set Intel QPI link 0 will be disabled.
22:20 RO-FW 000b PCIE_SPARE
19 RO-FW 0b
PCIE_DISNTB
Disable NTB support
18 RO-FW 0b
PCIE_DISROL
Disable Raid-on-load
17 RO-FW 0b
PCIE_DISLTSX
Disable LTSX
16 RO-FW 0b Reserved
15 RO-FW 0b
PCIE_DISPCIEG3
Disable PCIe Gen 3
14 RO-FW 0b
PCIE_DISDMA
Disable DMA engine and supporting functionality
13 RO-FW 0b
PCIE_DISDMI
Disable DMI interface
12:3 RO-FW 0h
PCIE_DISXPDEV
Disable specific PCIe port (example: 2x20 (EP), 1x20(EN2), 2x20 (EN1) speed
supported here)
2:1 RO-FW 00b
PCIE_DISx16
Disable the PCIe x16 ports (limit to x8’s only)
0RO-FW 0b
PCIE_DISWS
Disable WS features such as graphics cards in PCIe gen 2 slots