Datasheet

Processor Uncore Configuration Registers
512 Datasheet, Volume 2
29:26 RO-FW 0000b
DMFC
This field controls which values may be written to the Memory Frequency Select
field 6:4 of the Clocking Configuration registers (MCHBAR Offset C00h). Any
attempt to write an unsupported value will be ignored.
[3:3] =If set, over-clocking is supported and bits [2:0] are ignored.
[2:0] =Maximum allowed memory frequency.
3b111 - up to DDR-1066 (4 x 266)
3b110 - up to DDR-1333 (5 x 266)
3b101 - up to DDR-1600 (6 x 266)
3b100 - up to DDR-1866 (7 x 266)
3b011 - up to DDR-2133 (8 x 266) -- reserved, not supported
3b010 - up to DDR-2400 (9 x 266) -- reserved, not supported
3b001 - up to DDR-2666 (10 x 266) -- reserved, not supported
3b000 - up to DDR-2933 (11 x 266) -- reserved, not supported
25:23 RO-FW 000b
MEM_PA_SIZE
Physical address size supported in the core low two bits (Assuming uncore is 44 by
default)
000 = 46
010 = 44
101 = 36
110 = 40
111 = 39
reserved
22:17 RO-FW 0h
SSKU_P0_RATIO
Max turbo Freq down ratio for soft bin
16:11 RO-FW 0h
SSKU_P1_RATIO
Guaranteed Freq ratio for soft bin
10 RO-FW 0b
SSKU_EN
Enable Soft SKU feature
9RO-FW0b
QOS_DIS
Disable Quality of Service
8RO-FW0b
CDD
0 = Device enabled.
1 = Device disabled.
uCode - GP# on WRMSR TURBO_POWER_CURRENT_LIMIT (TDC and TDP limits)
7RO-FW0b
X2APIC_EN
Enable Extended APIC support.
When set it enables the support of x2APIC (Extended APIC) in the core and
unCore.
6RO-FW0b
CPU_HOT_ADD_EN
Intel Trusted Execution Technology for Servers - ENABLE CPU HOT ADD
5RO-FW0b
PWRBITS_DIS
0 = Power features activated during reset
1 = Power features (especially clock gating) are not activated
4RO-FW0b
GV3_DIS
Disable GV3. Does not allow for the writing of the IA32_PERF_CONTROL register
in order to change ratios
3:2 RO-FW 00b
PPPE
PPPE_ENABLE
1RO-FW0b
CORE_RAS_EN
Enable Data Poisoning, MCA recovery
0RO-FW0b
DCA_EN
DCA Enable
CAPID1
Bus: 1 Device: 10 Function: 3 Offset: 88h
Bit Attr
Reset
Value
Description