Datasheet

Datasheet, Volume 2 511
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Processor Uncore Configuration Registers
4.4.5.4 CAPID1 Register
This register is a processor Capability Register used to expose to BIOS for SKU
differentiation.
12 RO-FW 0b
HT_DIS
Disable multi threading
11:9 RO-FW 000b
LLC_WAY_EN: Enable LLC ways
Value Cache Size
’000 0.5 M (4 lower ways)
’001 1 M (8 lower ways)
’010 1.5 M (12 lower ways)
’011 2 M (16 lower ways)
’100 2.5M (20 lower ways)
8RO-FW 0b
PRG_TDP_LIM_EN
Allows usage of TURBO_POWER_LIMIT MSRs
7:5 RO-FW 000b
CACHESZ: Minimal LLC size/ways.
Can be upgraded through SSKU up to LLC_WAYS_EN.
Value LLC Size per slice (Enabled ways per slice)
’000 0.5 M (4 lower ways)
’001 1 M (8 lower ways)
’010 1.5 M (12 lower ways)
’011 2 M (16 lower ways)
’100 2.5M (20 lower ways)
4RO-FW 0b
PKGTYP
Package Type
3RO-FW 0b
DE_SKTR_EP4S
Socket R, Efficient performance four socket configuration
2RO-FW 0b
DE_SKTR_EP2S
Socket R, Efficient performance two socket configuration
1RO-FW 0b
DE_SKTB2_EN
Socket B2, EN2 (entry level 2) package configuration
0RO-FW 0b
DE_SKTB2_UP
Socket B2, EN1 (entry level 1) package configuration
CAPID0
Bus: 1 Device: 10 Function: 3 Offset: 84h
Bit Attr
Reset
Value
Description
CAPID1
Bus: 1 Device: 10 Function: 3 Offset: 88h
Bit Attr
Reset
Value
Description
31 RO-FW 0b
DIS_MEM_MIRROR
Disable memory channel mirroring mode.
30 RO-FW 0b Reserved