Datasheet

Processor Uncore Configuration Registers
510 Datasheet, Volume 2
4.4.5.3 CAPID0 Register
This register is a processor Capability Register used to expose to BIOS for SKU
differentiation.
CAPID0
Bus: 1 Device: 10 Function: 3 Offset: 84h
Bit Attr
Reset
Value
Description
31 RO-FW 0b
PCLMULQ_DIS
Disable PCLMULQ instructions
30 RO-FW 0b
DCU_MODE
0 = Normal
1 = 16K 1/2 size ECC mode
29 RO-FW 0b
PECI_EN
Enable PECI to the processor
28 RO-FW 0b
ART_DIS
SparDisable support for Always Running APIC Timer.
Disable the ART (Always Running APIC Timer) function in the APIC (enable legacy
timer)
27 RO-FW 0b
SLC64_DIS
Disable Segment-Limit Checking 64-Bit Mode – Segment limit checks also in long
mode (currently only supported in compatibility mode)
26 RO-FW 0b
GSSE256_DIS
Disable all GSSE instructions and Disables setting GSSE
XFeatureEnabledMask[GSSE] bit.
25 RO-FW 0b
XSAVEOPT_DIS
Disable XSAVEOPT.
24 RO-FW 0b
XSAVE_DIS
Disable the following instructions: XSAVE, XSAVEOPT, XRSTOR, XSETBV, and
XGETBV.
23 RO-FW 0b
AES_DIS
Disable AES
22 RO-FW 0b
TSC_DEADLINE_DIS
APIC timer last tick relative mode:
Disable support for TSC Deadline
21 RO-FW 0b Reserved
20 RO-FW 0b Reserved
19 RO-FW 0b Reserved
18 RO-FW 0b
SMX_DIS
Disable SMX
17 RO-FW 0b
VMX_DIS
Disable VMX
16 RO-FW 0b
CORECONF_RES12
Core configuration reserved bit 12
15 RO-FW 0b
VT_X3_EN
Enable Intel VT-x3
14 RO-FW 0b
VT_REAL_MODE
Intel VT Real mode
13 RO-FW 0b
VT_CPAUSE_EN
Enable CPAUSE – conditional PAUSE loop exiting; New VMX control to allow exit on
PAUSE loop that are longer than a specified Window