Datasheet

Datasheet, Volume 2 51
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Processor Integrated I/O (IIO) Configuration Registers
3.2.4.5 RID—Revision Identification Register
3.2.4.6 CCR—Class Code Register
3.2.4.7 CLSR—Cacheline Size Register
RID
Bus: 0 Device: 0 Function: 0 Offset: 08h
Bus: 0 Device: 1 Function: 0–1 Offset: 08h
Bus: 0 Device: 2 Function: 0–3 Offset: 08h
Bus: 0 Device: 3 Function: 0–3 Offset: 08h
Bit Attr
Reset
Value
Description
7:0 RO 00h
Revision Identification
Reflects the Uncore Revision ID after reset.
Reflects the Compatibility Revision ID after BIOS writes 69h to any RID register in
any processor function.
Implementation Note: Read and write requests from the host to any RID
register in any processor function are re-directed to the IIO cluster. Accesses to
the CCR field are also redirected due to DWord alignment. It is possible that JTAG
accesses are direct; thus, will not always be redirected.
CCR
Bus: 0 Device: 0 Function: 0 Offset: 09h
Bus: 0 Device: 1 Function: 0–1 Offset: 09h
Bus: 0 Device: 2 Function: 0–3 Offset: 09h
Bus: 0 Device: 3 Function: 0–3 Offset: 09h
Bit Attr
Reset
Value
Description
23:16 RO 06h
Base Class
For Root ports (including the root port mode operation of DMI and NTB ports), this
field is hardwired to 06h indicating it is a Bridge Device.
15:8 RO 04h
Sub-Class
For Root ports, this field defaults to 04h indicating PCI-PCI bridge. This register
changes to the sub-class of 00h to indicate Host Bridge, when bit 0 in the
MISCCTRLSTS register is set.
7:0 RO 00h
Register-Level Programming Interface
This field is hardwired to 00h for PCI Express ports.
CLSR
Bus: 0 Device: 0 Function: 0 Offset: 0Ch
Bus: 0 Device: 1 Function: 0–1 Offset: 0Ch
Bus: 0 Device: 2 Function: 0–3 Offset: 0Ch
Bus: 0 Device: 3 Function: 0–3 Offset: 0Ch
Bit Attr
Reset
Value
Description
7:0 RW 0h
Cacheline Size
This register is set as RW for compatibility reasons only. Cacheline size for the
processor is always 64B. IIO hardware ignores this setting.