Datasheet

Datasheet, Volume 2 505
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Processor Uncore Configuration Registers
4.4.4.14 PERF_P_LIMIT_CONTROL Register
This register is BIOS configurable. Dual mapping will prevent additional fast path
events or polling needs from PCODE. Hardware does not use the CSR input, it is
primarily used by PCODE. Note that PERF_P_LIMIT_CLIP must be nominally configured
to guaranteed frequency + 1, if turbo related actions are needed in slave sockets.
PERF_P_LIMIT_CONTROL
Bus: 1 Device: 10 Function: 2 Offset: E4h
Bit Attr
Reset
Value
Description
31:19 RO-V 0FA0h
I-Turbo Wait Period
Time period in ms to wait before granting Turbo, from the time the first Turbo is
requested.
Reset Value = 4 seconds.
18:13 RW-V 0h
Perf_P_Limit_Threshold
Threshold values
12 RO-V 0b
I-Turbo Enable
Enable bit for I-Turbo Feature.
11:6 RW-V 0h
Perf_P_Limit_Clip
Clip values to be used for Clip/Threshold Mode
5RW-V 0b
Disable_PERF_P_Input
Disable input from Perf-P limit into the I-Turbo algorithm.
4:3 RW-V 00b Reserved
2:1 RW-V 00b
Resolution_mode
Resolution mode determines the algorithm used in master.
00 = Maximum p-state
01 = Max clip = Max valued clip to Perf_P_Limit_Clip
10 = Threshold = If any value exceeds threshold, force output Perf_P_Limit_Clip
11 = Average = Average P-State
0RW-V 0b
Perf_P_Limit_En
Enable bit for enabling Performance P-Limit function,