Datasheet

Processor Uncore Configuration Registers
504 Datasheet, Volume 2
4.4.4.12 DRAM_PLANE_POWER_LIMIT—DRAM Plane Power Limit Register
This register is used by BIOS/OS/Integrated Graphics Driver/CPM Driver to limit the
power budget of DRAM Plane.
The overall package turbo power limitation is controlled by
DRAM_PLANE_POWER_LIMIT.
4.4.4.13 DRAM_RAPL_PERF_STATUS—DRAM RAPL Perf Status Register
This register is used by Pcode to report DRAM Plane Power limit violations in the
Platform PBM.
Dual mapped as PCU IOREG
DRAM_PLANE_POWER_LIMIT
Bus: 1 Device: 10 Function: 2 Offset: C8h
Bit Attr
Reset
Value
Description
63:32 RV 0h Reserved
31 RW-KL 0b
Primary Plane Power Limit Lock
When this bit is set, all settings in this register are locked and are treated as Read
Only.
30:24 RV 0h Reserved
23:17 RW-L 00h
Control Time Windows
x = CTRL_TIME_WIN[23:22]
y = CTRL_TIME_WIN[21:17]
The timing interval window is Floating Point number given by 1.x * power(2,y).
The unit of measurement is defined in
PACKAGE_POWER_SKU_UNIT_MSR[TIME_UNIT].
The maximal time window is bounded by
PACKAGE_POWER_SKU_MSR[PKG_MAX_WIN]. The minimum time window is 1
unit of measurement (as defined above).
16 RO 0b
RESERVED
Reserved
15 RW-L 0b
Power Limitation Control Enable
This bit must be set in order to limit the power of the DRAM power plane.
0 = DRAM power plane power limitation is disabled
1 = DRAM power plane power limitation is enabled
14:0 RW-L 0000h
DRAM Power Plane Power Limitation
This is the power limitation on the IA cores power plane.
The unit of measurement is defined in
DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].
DRAM_RAPL_PERF_STATUS
Bus: 1 Device: 10 Function: 2 Offset: D8h
Bit Attr
Reset
Value
Description
63:16 RV 0h Reserved
15:0 RO-V 0000h
Power Limit Violation Counter
This field reports the number of times the Power limiting algorithm had to clip the
power limit due to hitting the lowest power state available.