Datasheet

Datasheet, Volume 2 503

Processor Uncore Configuration Registers
4.4.4.10 DRAM_ENERGY_STATUS Register
DRAM energy consumed by all the DIMMS in all the Channels. The counter will wrap
around and continue counting when it reaches its limit.
The energy status is reported in units which are defined in
DRAM_POWER_INFO_UNIT_MSR[ENERGY_UNIT].
The data is updated by PCODE and is Read Only for all SW.
4.4.4.11 DRAM_ENERGY_STATUS_CH[0:3]—DRAM Energy Status 
CH0 Register
DRAM energy consumed by all the DIMMS in Channel0. The counter will wrap around
and continue counting when it reaches its limit.
The energy status is reported in units which are defined in
DRAM_POWER_INFO_UNIT_MSR[ENERGY_UNIT].
The data is updated by PCODE and is Read Only for all SW.
DRAM_ENERGY_STATUS
Bus: 1 Device: 10 Function: 2 Offset: A0h
Bit Attr
Reset
Value
Description
63:32 RV 0h Reserved
31:0 RO-V
000000
00h
Energy Value
DRAM_ENERGY_STATUS_CH[0:3]
Bus: 1 Device: 10 Function: 2 Offset: A8h, B0h, B8h, C0h
Bit Attr
Reset
Value
Description
63:32 RV 0h Reserved
31:0 RO-V
000000
00h
Energy Value