Datasheet

Processor Uncore Configuration Registers
502 Datasheet, Volume 2
4.4.4.8 PACKAGE_RAPL_PERF_STATUS Register
This register is used by Pcode to report Package Power limit violations in the Platform
PBM.
4.4.4.9 DRAM_POWER_INFO Register
This register defines allowed DRAM power and timing parameters.
PCODE will update the contents of this register.
PACKAGE_RAPL_PERF_STATUS
Bus: 1 Device: 10 Function: 2 Offset: 88h
Bit Attr
Reset
Value
Description
63:32 RV 0h Reserved
31:0 RO-V
000000
00h
Power Limit Throttle Counter
This field reports the number of times the Power limiting algorithm had to clip the
power limit due to hitting the lowest power state available.
Accumulated PACKAGE throttled time
DRAM_POWER_INFO
Bus: 1 Device: 10 Function: 2 Offset: 90h
Bit Attr
Reset
Value
Description
63 RW-KL 0b
Lock
Lock bit to lock the Register.
62:55 RV 0h Reserved
54:48 RW-L 28h
Maximal Time Window
The maximal time window allowed for the DRAM. Higher values will be clamped to
this value.
x = PKG_MAX_WIN[54:53]
y = PKG_MAX_WIN[52:48]
The timing interval window is Floating Point number given by 1.x * power(2,y).
The unit of measurement is defined in
DRAM_POWER_INFO_UNIT_MSR[TIME_UNIT].
47 RV 0h Reserved
46:32 RW-L 0258h
Maximal Package Power
The maximal power setting allowed for DRAM. Higher values will be clamped to
this value. The maximum setting is typical (not guaranteed).
The units for this value are defined in
DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].
31 RV 0h Reserved
30:16 RW-L 0078h
Minimal DRAM Power
The minimal power setting allowed for DRAM. Lower values will be clamped to
this value. The minimum setting is typical (not guaranteed).
The units for this value are defined in
DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].
15 RV 0h Reserved
14:0 RW-L 0118h
Spec DRAM Power
The specification power allowed for DRAM. The TDP setting is typical (not
guaranteed).
The units for this value are defined in
DRAM_POWER_INFO_UNIT_MSR[PWR_UNIT].