Datasheet
Datasheet, Volume 2 501
Processor Uncore Configuration Registers
4.4.4.6 PKG_CST_ENTRY_CRITERIA_MASK Register
This register is used to configure which events will be used as a gate for PC3 entry.
Expectation is that IOS will write this register based on the system config and devices
in the system.
It is expected that disabled Intel QPI/PCIe links must report L1.
4.4.4.7 PRIMARY_PLANE_RAPL_PERF_STATUS Register
This register is used by Pcode to report QOS and Power limit violations in the Platform
PBM.
Dual mapped as PCU IOREG
PKG_CST_ENTRY_CRITERIA_MASK
Bus: 1 Device: 10 Function: 2 Offset: 7Ch
Bit Attr
Reset
Value
Description
31:29 RW 000b Reserved
28 RW 1b
DRAM_in_SR
When set to 1, DRAM must be in SR.
27:26 RW 00b Reserved
25 RW 1b
QPI_1_in_L1
When set to 1, QPI_1 is required to be in L1.
24 RW 1b
QPI_0_in_L1
When set to 1, QPI_0 must be in L1
23 RW 0b
QPI_1_in_L0s
When set to 1, QPI_1 must be in L0s or L1.
22 RW 0b
QPI_0_in_L0s
When set to 1, QPI_0 must be in L0s or L1.
21:11 RW 000h
PCIe_in_L1
MSB = PCIe10. LSB=PCIe0.
10:0 RW 000h
PCIe_in_L0s
MSB = PCIe_10. LSB = PCIe_0.
PRIMARY_PLANE_RAPL_PERF_STATUS
Bus: 1 Device: 10 Function: 2 Offset: 80h
Bit Attr
Reset
Value
Description
63:32 RV 0h Reserved
31:0 RO-V
000000
00h
Power Limit Throttle Counter
This field reports the number of times the Power limiting algorithm had to clip the
power limit due to hitting the lowest power state available.
Accumulated PRIMARY_PLANE throttled time