Datasheet

Processor Integrated I/O (IIO) Configuration Registers
50 Datasheet, Volume 2
12 RW1C 0b
Received Target Abort
This bit is set when a device experiences a completer abort condition on a
transaction it mastered on the primary interface (uncore internal bus). Certain
errors might be detected right at the PCI Express interface and those transactions
might not propagate to the primary interface before the error is detected (for
example, accesses to memory above VTBAR). Such errors do not cause this bit to
be set, and are reported using the PCI Express interface error bits (secondary
status register).
Conditions that cause bit 12 to be set, include:
• Device receives a completion on the primary interface (internal bus of uncore)
with completer abort completion Status. This includes CA status received on
the primary side of a PCI Express port on peer-to-peer completions also.
11 RW1C 0b
Signaled Target Abort
This bit is set when a root port signals a completer abort completion status on the
primary side (internal bus of uncore). This condition includes a PCI Express port
forwarding a completer abort status received on a completion from the secondary.
10:9 RO 0h
DEVSEL# Timing
Not applicable to PCI Express. Hardwired to 0.
8RW1C 0b
Master Data Parity Error
This bit is set by a root port if the Parity Error Response bit in the PCI Command
register is set and it either receives a completion with poisoned data from the
primary side or it forwards a packet with data (including MSI writes) to the
primary side with poison.
7RO0b
Fast Back-to-Back
Not applicable to PCI Express. Hardwired to 0.
6RO0bReserved
5RO0b
PCI Bus 66 MHz Capable
Not applicable to PCI Express. Hardwired to 0.
4RO1b
Capabilities List
This bit indicates the presence of a capabilities list structure.
3RO-V0b
INTx Status
This read-only bit reflects the state of the interrupt in the PCI Express Root Port.
Only when the Interrupt Disable bit in the command register is a 0 and this
Interrupt Status bit is a 1, will this device generate INTx interrupt. Setting the
Interrupt Disable bit to a 1 has no effect on the state of this bit. This bit does not
get set for interrupts forwarded to the root port from downstream devices in the
hierarchy. When MSI are enabled, Interrupt status should not be set.
The intx status bit should be de-asserted when all the relevant events (RAS
errors/HP/link change status/PM) internal to the port using legacy interrupts are
cleared by software.
2:0 RV 0h Reserved
PCISTS
Bus: 0 Device: 0 Function: 0 Offset: 06h
Bus: 0 Device: 1 Function: 0–1 Offset: 06h
Bus: 0 Device: 2 Function: 0–3 Offset: 06h
Bus: 0 Device: 3 Function: 0–3 Offset: 06h
Bit Attr
Reset
Value
Description