Datasheet
Datasheet, Volume 2 5
3.2.4.89 PCIE_IOU_BIF_CTRL—PCIe* Port Bifurcation Control Register....... 108
3.2.4.90 PXP2CAP—Secondary PCI Express* Extended Capability
Header Register...................................................................... 109
3.2.4.91 LNKCON3—Link Control 3 Register............................................ 109
3.2.5 PCI Express* and DMI2 Error Registers ................................................... 110
3.2.5.1 ERRINJCAP—PCI Express* Error Injection Capability Register........ 110
3.2.5.2 ERRINJHDR—PCI Express* Error Injection Capability
Header Register...................................................................... 110
3.2.5.3 ERRINJCON—PCI Express* Error Injection Control Register .......... 111
3.2.5.4 CTOCTRL—Completion Timeout Control Register ......................... 111
3.2.5.5 XPCORERRSTS—XP Correctable Error Status Register .................. 112
3.2.5.6 XPCORERRMSK—XP Correctable Error Mask Register ................... 112
3.2.5.7 XPUNCERRSTS—XP Uncorrectable Error Status Register............... 113
3.2.5.8 XPUNCERRMSK—XP Uncorrectable Error Mask Register ................ 113
3.2.5.9 XPUNCERRSEV—XP Uncorrectable Error Severity Register ............ 114
3.2.5.10 XPUNCERRPTR—XP Uncorrectable Error Pointer Register .............. 114
3.2.5.11 UNCEDMASK—Uncorrectable Error Detect Status Mask Register .... 115
3.2.5.12 COREDMASK—Correctable Error Detect Status Mask Register ....... 115
3.2.5.13 RPEDMASK—Root Port Error Detect Status Mask Register............. 116
3.2.5.14 XPUNCEDMASK—XP Uncorrectable Error Detect Mask Register...... 116
3.2.5.15 XPCOREDMASK—XP Correctable Error Detect Mask Register ......... 117
3.2.5.16 XPGLBERRSTS—XP Global Error Status Register.......................... 117
3.2.5.17 XPGLBERRPTR—XP Global Error Pointer Register ......................... 118
3.2.5.18 LNERRSTS—Lane Error Status Register...................................... 118
3.2.5.19 LER_CAP—Live Error Recovery Capability Register....................... 119
3.2.5.20 LER_HDR—Live Error Recovery Capability Header Register ........... 119
3.2.5.21 LER_CTRLSTS—Live Error Recovery Control and Status Register ... 119
3.2.5.22 LER_UNCERRMSK—Live Error Recovery Uncorrectable
Error Mask Register................................................................. 120
3.2.5.23 LER_XPUNCERRMSK—Live Error Recovery XP Uncorrectable
Error Mask Register................................................................. 120
3.2.5.24 LER_RPERRMSK—Live Error Recovery Root Port Error
Mask Register......................................................................... 121
3.2.6 PCI Express* Lane Equalization Registers ................................................ 121
3.2.6.1 LN[0:3]EQ—Lane 0 through Lane 3 Equalization
Control Register...................................................................... 121
3.2.6.2 LN[4:7]EQ—Lane 4 through Lane 7 Equalization Control Register .. 122
3.2.6.3 LN[8:15]EQ—Lane 8 though Lane 15 Equalization Control Register 124
3.2.7 PCI Express* and DMI2 Perfmon ............................................................ 125
3.2.7.1 XPPMDL[0:1]—XP PM Data Low Bits Register.............................. 125
3.2.7.2 XPPMCL[0:1]—XP PM Compare Low Bits Register ........................ 125
3.2.7.3 XPPMDH—XP PM Data High Bits Register.................................... 126
3.2.7.4 XPPMCH—XP PM Compare High Bits Register .............................. 126
3.2.7.5 XPPMR[0:1]—XP PM Response Control Register........................... 127
3.2.7.6 XPPMEVL[0:1]—XP PM Events Low Register................................ 130
3.2.7.7 XPPMEVH[0:1]—XP PM Events High Register .............................. 132
3.2.7.8 XPPMER[0:1]—XP PM Resource Events Register.......................... 133
3.2.8 DMI Root Complex Register Block (RCRB)................................................ 134
3.2.8.1 DMIVC0RCAP—DMI VC0 Resource Capability Register.................. 135
3.2.8.2 DMIVC0RCTL—DMI VC0 Resource Control Register...................... 135
3.2.8.3 DMIVC0RSTS—DMI VC0 Resource Status Register....................... 136
3.2.8.4 DMIVC1RCAP—DMI VC1 Resource Capability Register.................. 136
3.2.8.5 DMIVC1RCTL—DMI VC1 Resource Control Register...................... 137
3.2.8.6 DMIVC1RSTS—DMI VC1 Resource Status Register....................... 138
3.2.8.7 DMIVCPRCAP—DMI VCP Resource Capability Register .................. 138
3.2.8.8 DMIVCPRCTL—DMI VCP Resource Control Register...................... 139
3.2.8.9 DMIVCPRSTS—DMI VCP Resource Status Register....................... 140
3.2.8.10 DMIVCMRCAP—DMI VCM Resource Capability Register................. 140
3.2.8.11 DMIVCMRCTL—DMI VCM Resource Control Register..................... 141
3.2.8.12 DMIVCMRSTS—DMI VCM Resource Status Register...................... 141
3.2.8.13 DMIRCLDECH—DMI Root Complex Link Declaration Register......... 142