Datasheet

Datasheet, Volume 2 499
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Processor Uncore Configuration Registers
4.4.4.4 GLOBAL_PKG_C_S_CONTROL Register
This register is in the PCU CR space. It contains information pertinent to the master
slave IPC protocol and global enable/disable for PK CST and SST. Expectation is that
BIOS will write this register during the Reset/Init flow.
22 RW-V 0b
Turbo Demotion Override Enable
0 = Disable override
1 = Enable override
21 RW-V 0b Reserved
20 RW-V 0b
Uncore_Perf_PLimit_Override_Enable
0 = Disable over ride
1 = Enable over ride
19:16 RW-V 0b Reserved
15 RW-V 0b
IO_BW_PLimit_Override_Enable
0 = Disable over ride
1 = Enable over ride
14:11 RV 0h Reserved
10 RW-V 0b
IMC_APM_Override_Enable
0 = Disable over ride
1 = Enable over ride
9:6 RV 0h Reserved
5RW-V 0b
IOM_APM_Override_Enable
0 = Disable over ride
1 = Enable over ride
4:1 RV 0h Reserved
0RW-V 0b
QPI_APM_Override_Enable
0 = Disable over ride
1 = Enable over ride
DYNAMIC_PERF_POWER_CTL
Bus: 1 Device: 10 Function: 2 Offset: 64h
Bit Attr
Reset
Value
Description
GLOBAL_PKG_C_S_CONTROL_REGISTER
Bus: 1 Device: 10 Function: 2 Offset: 6Ch
Bit Attr
Reset
Value
Description
31:15 RW 00000h Reserved
14:12 RW 000b
Master_NID
Master socket NID. Can also be determined from the Socket0 entry in the NID
MAP register.
11 RW 0b Reserved
10:8 RW 000b
My_NID
NID of this socket.
7:3 RW 0h Reserved
2RW0b
Am_I_Master
If this bit is set, socket is master. Master socket will be the leady socket. BIOS will
set this bit in the legacy socket.
1:0 RW 0b Reserved