Datasheet

Datasheet, Volume 2 497
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Processor Uncore Configuration Registers
4.4.3.12 RINGTIMERS—RING Timers Register
RING Timers in 10n s granularity.
4.4.3.13 BANDTIMERS—PLL Self Banding Timers Register
MPLL and PPLL time to complete the self-banding process.
The units are in 10 ns (100 MHz) granularity.
RINGTIMERS
Bus: 1 Device: 10 Function: 1 Offset: C4h
Bit Attr
Reset
Value
Description
31:22 RW-L 200h
RCLK PLL SFR Timer
This field is used to generate a deterministic time for SFR (5 uSec).
The value is defined in BCLK granularity (10 ns units). The default value of 200h
corresponds to 5.12 uSec.
21:10 RW-L 76Ch
RCLK PLL Reset Timer
This field is used to generate a deterministic RCLK PLL lock signal for Reset. The
value should account for PLL lock (with banding time):
• PLL Lock = 2.5 uSec (150 cycles for phase acquisition + 64 cycles lock timer)
• Self Banding = 14 uSec
The value is defined in BCLK granularity (10ns units). The default value of 76Ch
corresponds to 19 uSec.
BANDTIMERS
Bus: 1 Device: 10 Function: 1 Offset: C8h
Bit Attr
Reset
Value
Description
31:16 RW-L 0640h
Memory PLL Banding Timer
The time it takes for the PLL to find the best band. This time is taken into account
on the first PLL lock (reset) and in any PLL lock if
PCU_MISC_ENABLE[LNPLLfastLockDisable] is set to 1b.
The HVM hander may program this timer to a low value to shorten the test time.
The default value corresponds to 16 us.
15:0 RW-L 2FA8h
PCIe and DMI PLL Banding Timer
The time it takes for the PLL to find the best band. This time is taken into account
on the first PLL lock (reset) and in any PLL lock if
PCU_MISC_ENABLE[LCPLLfastLockDisable] is set to 1b.
The HVM hander may program this timer to a low value to shorten the test time.
The default value corresponds to 122 us.