Datasheet

Processor Uncore Configuration Registers
496 Datasheet, Volume 2
4.4.3.10 M_COMP—Memory COMP Control Register
4.4.3.11 SAPMTIMERS—System Agent Power Management Timers Register
SAPM timers in 10 ns (100 MHz) units.
PCODE will sample this register at the end of Phase 4.
M_COMP
Bus: 1 Device: 10 Function: 1 Offset: B8h
Bit Attr
Reset
Value
Description
31:9 RV 0h Reserved
8RW1S0b
Force COMP Cycle
Writing 1 to this field triggers a COMP cycle. HW will reset this bit when the COMP
cycle ends.
7:5 RV 0h Reserved
4:1 RW-L Dh
Periodic COMP Interval
This field indicates the period of RCOMP. The time is indicated by
power(2,COMP_INTERVAL) * 10.24 usec.
The default value of Dh corresponds to ~84 ms.
0RW-L 0b
COMP Disable
Disable periodic COMP cycles
0 = Enabled
1 = Disabled
SAPMTIMERS
Bus: 1 Device: 10 Function: 1 Offset: C0h
Bit Attr
Reset
Value
Description
31:16 RW-L 00FAh
Memory PLL Timer
This field is used to generate a deterministic memory PLL lock signal. The value
should allow SFR lock + PLL lock (without PLL banding time) + DQ clock
compensation.
•SFR lock = 5 us
• PLL lock = 2.5 us (150 cycles for phase acquisition + 64 cycles lock timer)
• D/Qclk compensation = 1.05 us (550 Dclk for DDR1067)
There is a strong relationship between this register value and
1. The latencies the PCU negotiate with the IO devices,
2. The display engine watermark values set by the graphics driver
The value is defined in granularity of BCLK (10ns). The default value of FAh
corresponds to 2.5 uSec.
PCODE assumes this field aligns with the similar field in
BANDTIMERS_1_10_1_CFG - c
15:8 RV 0h Reserved