Datasheet

Datasheet, Volume 2 495
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Processor Uncore Configuration Registers
12 RW-L 1b
Non-Snoop Wakeup Triggers Self Refresh Exit
When this bit is set to 1b, a Non-Snoop wakeup signal from PCH sideband
indication will cause the PCU to force the MC to exit from Self-Refresh. Otherwise,
the Non-Snoop indication will not affect the Self Refresh exit policy.
11 RW-L 0b
Ungate System Agent Clock on Self Refresh Exit
The Display Engine can indicate to the PCU that it wants the Memory Controller to
exit self-refresh.
When this bit is set to 1b, this request from the Display Engine will cause FCLK to
be ungated. Otherwise, this request from the Display Engine has no effect on
FCLK gating.
10 RW-L 0b
Memory DLL Shutdown Sensitivity
This bit indicates when the Memory Master DLL may be shutdown based on link
active power states.
0 = Memory DLL may be shut down in L1 and deeper sleep states.
1 = Memory DLL may be shut down in L0s and deeper sleep states.
9RW-L 0b
Memory PLL Shutdown Sensitivity
This bit indicates when the Memory PLLs (MCPLL and GDPLL) may be shutdown
based on link active power states.
0 = Memory PLLs may be shut down in L1 and deeper sleep states.
1 = Memory PLLs may be shut down in L0s and deeper sleep states.
8RW-L 1b
System Agent Clock Gating Sensitivity
This bit indicates when the System Agent clock gating is possible based on link
active power states.
0 = System Agent clock gating is allowed in L1 and deeper sleep states.
1 = System Agent clock gating is allowed in L0s and deeper sleep states.
Note: This bit is redundant, since L0s can never allow Fclk gating, since PPLL is
on.
7:4 RV 0h Reserved
3RW-L 1b
Intel QPI PLL Shutdown Enable
This bit is used to enable shutting down the Intel QPI PLL.
0 = PLL shutdown is not allowed
1 = PLL shutdown is allowed
2RW-L 1b
PCIe PLL Shutdown Enable
This bit is used to enable shutting down the PCIe/DMI PLL.
0 = PLL shutdown is not allowed
1 = PLL shutdown is allowed
1RW-L 1b
Memory PLLs Shutdown Enable
This bit is used to enable shutting down the Memory Controller PLLs (MCPLL and
GDPLL).
0 = PLL shutdown is not allowed
1 = PLL shutdown is allowed
0RW-L 0b
System Agent Clock Gating Enable
This bit is used to enable or disable the System Agent Clock Gating (FCLK).
0 = SA Clock Gating is Not Allowed
1 = SA Clock Gating is Allowed
SAPMCTL
Bus: 1 Device: 10 Function: 1 Offset: B0h
Bit Attr
Reset
Value
Description