Datasheet

Processor Uncore Configuration Registers
494 Datasheet, Volume 2
4.4.3.9 SAPMCTL—System Agent Power Management Control Register
PCODE will sample this register at the end of Phase 4.
SAPMCTL
Bus: 1 Device: 10 Function: 1 Offset: B0h
Bit Attr
Reset
Value
Description
31 RW-KL 0b
Lock Indication
When set to 1b this bit locks various PM registers.
30 RW-L 0b
SetVID Decay Disable
This bit is used by BIOS to disable SETVID Decay to enable use of VR12 designs
that do not support decay function.
0 = Enable Decay (Reset Value)
1 = Disable Decay
29 RW-L 1b
QPI_L0S_PLL_SEN_ENABLE
This bit is used by BIOS to disable Intel QPI L0S link state from playing any role in
TurnPLL On/Srexit equation in ptpc_sapm.vs.
1 = Enable QPI_L0s in TurnPLL On/Srexit equations.(Reset Value)
0 = Disable QPI_L0s in TurnPLL On/Srexit equations
28 RW-L 1b
QPI_L0_PLL_SEN_ENABLE
This bit is used by BIOS to disable Intel QPI L0 link state from playing any role in
TurnPLL On/Srexit equation in ptpc_sapm.vs.
1 = Enable QPI_L0 in TurnPLL On/Srexit equations.(Reset Value)
0 = Disable QPI_L0 in TurnPLL On/Srexit equations
27 RW-L 1b
IIO_L0S_PLL_SEN_ENABLE
This bit is used by BIOS to disable IIO L0S link state from playing any role in
TurnPLL On/Srexit equation in ptpc_sapm.vs.
1 = Enable IIO_L0S in TurnPLL On/Srexit equations.(Reset Value)
0 = Disable IIO_L0S in TurnPLL On/Srexit equations
26 RW-L 1b
IIO_L0_PLL_SEN_ENABLE
This bit is used by BIOS to disable IIO L0 link state from playing any role in
TurnPLL On/Srexit equation in ptpc_sapm.vs.
1 = Enable IIO_L0 in TurnPLL On/Srexit equations.(Reset Value)
0 = Disable IIO_L0 in TurnPLL On/Srexit equations
25:16 RV 0h Reserved
15 RW-L 0b
Memory DLL On When Display Engine is Active
Force memory master DLL on when the Display Engine is active. This includes
cases where memory is not accessed.
This bit has to be set only if there are issues with the memory DLL wakeup based
on the Self Refresh exit indication from Display Engine.
0 = Display Engine wakes up memory DLL using the Self Refresh exit indication
only
1 = Force Memory DLL on when the Display Engine is active
14 RW-L 0b
Memory PLL On When Display Engine is Active
Force Memory PLLs (MCPLL and GDPLL) on when the Display Engine is active. This
includes cases where memory is not accessed.
This bit has to be set only if there are issues with the Memory PLL wakeup based
on the Self Refresh exit indication from Display Engine.
0 = Display Engine wakes up Memory PLLs using the Self Refresh exit indication
only
1 = Force Memory PLLs on when the Display Engine is active
13 RW-L 1b
Ungate System Agent Clock When Memory PLL is On
When this bit is set to 1b, FCLK will never be gated when the memory controller
PLL is ON. Otherwise, FCLK gating policies are not affected by the locking of the
memory controller PLLs.