Datasheet

Datasheet, Volume 2 493
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Processor Uncore Configuration Registers
4.4.3.7 MC_BIOS_REQ—MC_BIOS_REQ Register
This register allows BIOS to request Memory Controller clock frequency.
4.4.3.8 CSR_DESIRED_CORES—Desired Cores Register
This register defines the number of cores/threads BIOS wants to exist on the next
reset. A processor reset must be used for this register to take effect. Programming this
register to a value higher than the product has cores should not be done.
This register is reset only by PWRGOOD.
MC_BIOS_REQ
Bus: 1 Device: 10 Function: 1 Offset: 98h
Bit Attr
Reset
Value
Description
31:6 RV 0b Reserved
5:0 RWS 00h
Request Data
These 6 bits are the data for the request.
The only possible request type is MC frequency request.
The encoding of this field is indicating the Dclk multiplier:
Binary Dec Dclk Equation Dclk freq. Qclk Freq.
’000000b 0d ---------------- MC PLL - shutdown ---------------------
...
’001000b 8d 8*66.66 MHz 533.33 MHz 1067.66 MHz
’001010b 10d 10*66.66 MHz 666.667 MHz 1333.33 MHz
’001100b 12d 12*66.66 MHz 800 MHz 1600 MHz
’001110b 14d 14*66.66 MHz 933.33 MHz 1866.67 MHz
’010000b 16d 16*66.66 MHz 1066.67 MHz 2133.33 MHz
...
CSR_DESIRED_CORES
Bus: 1 Device: 10 Function: 1 Offset: A4h
Bit Attr
Reset
Value
Description
31 RWS-KL 0b
Lock
Once written to a 1, changes to this register cannot be done. Cleared only by a
power-on reset .
30 RWS-L 0b
SMT Disable
Disable simultaneous multithreading in all cores if this bit is set to 1.
29:16 RV 0h Reserved
15:0 RWS-L 0000h
Cores Off Mask
BIOS will set this bit to request that the matching core should not be activated
coming out of reset.
The default value of this registers means that all cores are enabled.
Restrictions: At least one core needs to be left active. Otherwise, FW will ignore
the setting altogether.