Datasheet

Processor Uncore Configuration Registers
492 Datasheet, Volume 2
4RW1S0b
Memory Calibration Done
Used to Facilitate handshake between BIOS and Pcode
Memory Calibration Done – DRAM power meter coeffs are now ready for sampling;
DRAM PWR Mtr runs only with OLTT up until this bit is set. Once this bit is set,
DRAM PWR MTR can start using the DRAM weights.
Usage:
This bit is used by BIOS to indicate to Pcode that it has completed running the
DRAM characterization workloads and has programmed the weights in Pcode
Memory using the BIOS to Pcode Mailbox.
When this bit is set by BIOS, Pcode will "lock" out the commands in the
BIOS2PCODE mailbox which were left available for BIOS to complete the DRAM
characterization.
Expectation is that Pcode will sample this bit every slow loop and when it detects it
to be 1, mailbox will be locked out completely and DRAM PBM and Power meter
features will become available.
Note: If this bit is not set to 1, DRAM PBM and power meter features will not
work.
3RW1S0b
PM Configuration Complete
Used to Facilitate handshake between BIOS and Pcode
Power-management configuration complete – all the configuration for EDP, PBM,
etc is complete. Following this point, a limited number of BIOS-to-Pcode mailbox
commands are still allowed.
2RW1S0b
Periodic RCOMP Start
Used to Facilitate handshake between BIOS and Pcode
Periodic RCOMP Start – Pcode starts issuing periodic RCOMPs from this point
forward
1RW1S0b
PkgS NID Config Complete
Used to Facilitate handshake between BIOS and Pcode
Node ID Configuration is Complete – allows pcode to get ready to receive a Reset
Warn; No power mgmt features running at all till this point.
If EXPECT_CPU_ONLY_RESET command was issued previously, then Pcode will
execute the CPU-Only reset when it sees RST_CPL_1 set
0RW1S0b
BIOS Initialization Complete
Traditional BIOS Done – Pcode samples all PM related registers at this time; No
power Mgmnt features before this point except Reset Warn; No Ratio change can
happen before this bit is set.
This bit is set by BIOS to indicate to the processor Power management function
that it has completed to set up all PM relevant configuration and allow processor
Power management function to digest the configuration data and start active PM
operation.
It is expected that this bit will be set just before BIOS transfer of control to the
OS.
0 = Not ready
1 = BIOS PM configuration complete
This is kept for backward-compatibility with A-step. If BIOS sets this bit, Pcode
interprets it as if RST_CPL_4:RST_CPL_1 (bits 4:1) are all set. In other words,
this bit supersedes all other bits. Pcode will ack this bit by setting
PCODE_INIT_DONE_4:PCODE_INIT_DONE (bits 12:8).
BIOS_RESET_CPL
Bus: 1 Device: 10 Function: 1 Offset: 94h
Bit Attr
Reset
Value
Description